SnesLab - User contributions [en]

TCALL (SPC700)

2026-06-06T12:10:04Z

Xetheria: capitalize other L

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|'''Vector Address'''
|+
|[[Implied]] (type 3)
|01
|1 byte
|8 cycles
|$FFDE
|+
|[[Implied]] (type 3)
|11
|1 byte
|8 cycles
|$FFDC
|+
|[[Implied]] (type 3)
|21
|1 byte
|8 cycles
|$FFDA
|+
|[[Implied]] (type 3)
|31
|1 byte
|8 cycles
|$FFD8
|+
|[[Implied]] (type 3)
|41
|1 byte
|8 cycles
|$FFD6
|+
|[[Implied]] (type 3)
|51
|1 byte
|8 cycles
|$FFD4
|+
|[[Implied]] (type 3)
|61
|1 byte
|8 cycles
|$FFD2
|+
|[[Implied]] (type 3)
|71
|1 byte
|8 cycles
|$FFD0
|+
|[[Implied]] (type 3)
|81
|1 byte
|8 cycles
|$FFCE
|+
|[[Implied]] (type 3)
|91
|1 byte
|8 cycles
|$FFCC
|+
|[[Implied]] (type 3)
|A1
|1 byte
|8 cycles
|$FFCA
|+
|[[Implied]] (type 3)
|B1
|1 byte
|8 cycles
|$FFC8
|+
|[[Implied]] (type 3)
|C1
|1 byte
|8 cycles
|$FFC6
|+
|[[Implied]] (type 3)
|D1
|1 byte
|8 cycles
|$FFC4
|+
|[[Implied]] (type 3)
|E1
|1 byte
|8 cycles
|$FFC2
|+
|[[Implied]] (type 3)
|F1
|1 byte
|8 cycles
|$FFC0
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[Direct Page Flag|P]]
|[[Break Flag|B]]
|[[Half-Carry Flag|H]]
|[[Interrupt Enable Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|.
|.
|.
|.
|.
|.
|.
|.
|}

'''TCALL''' (Table CALL) is an [[SPC700]] instruction that calls a subroutine whose 16-bit address is stored in the [[uppermost page]]. The low byte of the address of the vector (pointer to subroutine) is a function of the high nybble of the opcode, equal to $DE - n*2. The high byte of the vector address is always $FF.

No flags are affected.

=== Syntax ===

<pre>
TCALL n
</pre>

where n is the '''vector call number''', a decimal integer from 0 to 15, which becomes the high nybble of the opcode.

=== See Also ===
* [[CALL]]
* [[PCALL]]
* [[RET]]
* [[SPC700/IPL ROM]]

=== External Links ===
* Official Nintendo documentation on TCALL: Table C-16 [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9]
* [https://www.romhacking.net/documents/197 anomie's SPC700 doc]
* https://forums.nesdev.org/viewtopic.php?t=13313

[[Category:ASM]]
[[Category:SPC700]]
[[Category:Subroutine Call Return Commands]]
[[Category:One-byte Instructions]]

Stack

2026-05-21T21:36:13Z

Xetheria: no stack base pointer

The '''Stack''' is a LIFO (last-in, first-out) buffer which remembers the state of subroutines that are currently executing.

On the [[65c816]], the stack is always in [[bank]] zero.[3] It can be thousands of bytes deep.[1]

In [[emulation mode]] it wraps within page one.[2]

The stack grows towards zero, but the most recently pushed byte is nontheless called the top of the stack.[4] These instructions push things to the stack:

* [[PEA]]
* [[PEI]]
* [[PER]]
* [[PHA]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]]
* [[PHX]]
* [[PHY]]
* [[JSR]]
* [[JSL]]
* [[COP]]
* [[BRK]]

PL* instructions take one cycle more than their PH* counterparts because they have to increment the stack pointer to point to the top element before it can be pulled, whereas push instructions pipeline the decrement of SP so that it overlaps the opcode fetch of the next instruction. These instructions pull things from the stack:

* [[PLA]]
* [[PLB]]
* [[PLD]]
* [[PLP]]
* [[PLX]]
* [[PLY]]
* [[RTS]]
* [[RTL]]
* [[RTI]]

Note the lack of [[PLK]]. PHS and PLS similarly do not exist, nor do any instructions performing the inverse of PEA, PEI, or PER. Unlike x86, there is also no stack base pointer.

=== See Also ===
* [[Stack Pointer]]

=== References ===
# Wilson, Garth. https://wilsonminesco.com/816myths
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.1.1
# section 2.11 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/33 page 33]

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Buffers]]

COP

2026-05-21T06:53:17Z

Xetheria: Undo revision 21257 by Xetheria (talk)

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|02
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|.
|.
|.
|.
|0
|1
|.
|.
|}

'''COP''' (Co-Processor) is a [[65c816]] instruction designed to run a co-processor command. COP triggers a software interrupt and control is routed to the COP handler, whose address is stored in the COP vector at $00:FFE4 (in [[native mode]] anyway, in emulation mode $FFF4 is used instead). The byte following the opcode is called the [[signature byte]] and is required by assemblers:
* Signature bytes of 00h to 7Fh can be programmer-defined
* Signature bytes of 80h to FFh are reserved for future microprocessors by the [https://www.westerndesigncenter.com/ Western Design Center][3]

The state of the [[interrupt disable flag]] has no effect on the behavior of COP although it will be set after COP runs.

Some examples of the kinds of microprocessors COP could be used to communicate with include:
* floating point
* graphics

The [[PBR]] is cleared, but in native mode its previous value is pushed to the [[stack]].

==== Syntax ====
<pre>
COP sig
</pre>

==== Cycle Skipped ====
* COP takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

[[File:cop.png]]

COP is not really used for anything on the SNES.[7]

=== See Also ===
* [[BRK]]
* [[RTI]]
* [[WDM]]
* [[Enhancement Chips]]

=== External Links ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/447 page 447] on COP
# [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n145 page 135] on COP
# section 7.15 of 65c816 datasheet
# snes9x implementation of COP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2738
# https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/misc
# https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts
# https://forums.nesdev.org/viewtopic.php?p=176406#p176406

[[Category:ASM]]
[[Category:65c816 additions]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

BRK

2026-05-21T06:51:14Z

Xetheria: Undo revision 21258 by Xetheria (talk)

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|00
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="9"|Flags Affected
|+
|
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]] / [[Break Flag|B]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[65c816 native mode]]
|.
|.
|.
|.
|0
|1
|.
|.
|+
|[[6502 emulation mode]]
|.
|.
|.
|1
|0
|1
|.
|.
|}

'''BRK''' (Break) is a 65x instruction that triggers a non-maskable software interrupt ([[Non-Maskable Interrupt|NMI]]). The byte following the opcode is called the [[signature byte]]. The state of the [[interrupt disable flag]] has no effect on the behavior of BRK although it will be set after BRK runs.

In [[native mode]] the [[program bank register]] is pushed to the [[stack]]. Then the [[program counter]] is incremented by two and then pushed to the stack. Then the [[status register]] (with the [[break flag]] set, if in emulation mode) is pushed to the stack. Then the interrupt disable flag is set. In native mode, the program bank register is then cleared.

Control is routed to the BRK handler, whose address is stored at the BRK vector:
* In native mode, this vector is at $00:FFE6.
* In emulation mode, this vector is at $FFFE.

==== Syntax ====
<pre>
BRK
BRK sig
</pre>

If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction. In this case the [[interrupt handler]] must decrement the [[return address]] on the [[stack]] so that the eventual [[RTI]] does not cause [[derailment]].

[[File:brk.png]]

BRK used to be considered a one-byte instruction in an early datasheet. On the NMOS 6502, BRK does not affect the decimal flag, but this likely only affects porting code from systems other than the NES because the NES does not have decimal mode anyway.

==== Cycle Skipped ====
* BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

=== See Also ===
* [[RTI]]
* [[BRK (SPC700)]]
* [[NMI]]
* [[IRQ]]
* [[COP]]
* [[WDM]]
* [[CLD]]
* [[SEI]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/436 page 436] on BRK
* Figure 13.3, Break Signature Byte Illustration, lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n136 page 126] on BRK
* 9.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n164 page 144] on BRK
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n265 page 252] on BRK
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n98 page 3-49] on BRK
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BRK
* Clark, Bruce. http://www.6502.org/tutorials/65c02opcodes.html#6
* https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

BRK

2026-05-21T06:39:59Z

Xetheria: /* External Links */ de n'd page number

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|00
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="9"|Flags Affected
|+
|
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]] / [[Break Flag|B]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[65c816 native mode]]
|.
|.
|.
|.
|0
|1
|.
|.
|+
|[[6502 emulation mode]]
|.
|.
|.
|1
|0
|1
|.
|.
|}

'''BRK''' (Break) is a 65x instruction that triggers a non-maskable software interrupt ([[Non-Maskable Interrupt|NMI]]). The byte following the opcode is called the [[signature byte]]. The state of the [[interrupt disable flag]] has no effect on the behavior of BRK although it will be set after BRK runs.

In [[native mode]] the [[program bank register]] is pushed to the [[stack]]. Then the [[program counter]] is incremented by two and then pushed to the stack. Then the [[status register]] (with the [[break flag]] set, if in emulation mode) is pushed to the stack. Then the interrupt disable flag is set. In native mode, the program bank register is then cleared.

Control is routed to the BRK handler, whose address is stored at the BRK vector:
* In native mode, this vector is at $00:FFE6.
* In emulation mode, this vector is at $FFFE.

==== Syntax ====
<pre>
BRK
BRK sig
</pre>

If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction. In this case the [[interrupt handler]] must decrement the [[return address]] on the [[stack]] so that the eventual [[RTI]] does not cause [[derailment]].

[[File:brk.png]]

BRK used to be considered a one-byte instruction in an early datasheet. On the NMOS 6502, BRK does not affect the decimal flag, but this likely only affects porting code from systems other than the NES because the NES does not have decimal mode anyway.

==== Cycle Skipped ====
* BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

=== See Also ===
* [[RTI]]
* [[BRK (SPC700)]]
* [[NMI]]
* [[IRQ]]
* [[COP]]
* [[WDM]]
* [[CLD]]
* [[SEI]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/436 page 436] on BRK
* Figure 13.3, Break Signature Byte Illustration, lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/126 page 126] on BRK
* 9.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n164 page 144] on BRK
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n265 page 252] on BRK
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n98 page 3-49] on BRK
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BRK
* Clark, Bruce. http://www.6502.org/tutorials/65c02opcodes.html#6
* https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

COP

2026-05-21T06:37:55Z

Xetheria: /* External Links */ de n'd page number

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|02
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|.
|.
|.
|.
|0
|1
|.
|.
|}

'''COP''' (Co-Processor) is a [[65c816]] instruction designed to run a co-processor command. COP triggers a software interrupt and control is routed to the COP handler, whose address is stored in the COP vector at $00:FFE4 (in [[native mode]] anyway, in emulation mode $FFF4 is used instead). The byte following the opcode is called the [[signature byte]] and is required by assemblers:
* Signature bytes of 00h to 7Fh can be programmer-defined
* Signature bytes of 80h to FFh are reserved for future microprocessors by the [https://www.westerndesigncenter.com/ Western Design Center][3]

The state of the [[interrupt disable flag]] has no effect on the behavior of COP although it will be set after COP runs.

Some examples of the kinds of microprocessors COP could be used to communicate with include:
* floating point
* graphics

The [[PBR]] is cleared, but in native mode its previous value is pushed to the [[stack]].

==== Syntax ====
<pre>
COP sig
</pre>

==== Cycle Skipped ====
* COP takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

[[File:cop.png]]

COP is not really used for anything on the SNES.[7]

=== See Also ===
* [[BRK]]
* [[RTI]]
* [[WDM]]
* [[Enhancement Chips]]

=== External Links ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/447 page 447] on COP
# [[Labiak]], [https://archive.org/details/Programming_the_65816/page/135 page 135] on COP
# section 7.15 of 65c816 datasheet
# snes9x implementation of COP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2738
# https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/misc
# https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts
# https://forums.nesdev.org/viewtopic.php?p=176406#p176406

[[Category:ASM]]
[[Category:65c816 additions]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

Pixel Processing Unit

2026-05-15T08:10:51Z

Xetheria: created page

#redirect [[Picture Processing Unit]]

BIT

2026-05-15T08:01:49Z

Xetheria: make effective address plus one super clear

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|89
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|2C
|3 bytes
|4 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|24
|2 bytes
|3 cycles*
|+
|[[Absolute Indexed by X]]
|3C
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|34
|2 bytes
|4 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|Addressing Mode
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[Immediate]]
|.
|.
|.
|.
|.
|.
|Z
|.
|+
|other
|N
|V
|.
|.
|.
|.
|Z
|.
|}

'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.

The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

Except in [[immediate addressing]], the most significant bit of the data located at the effective address (or effective address plus one) is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].

==== Syntax ====
<pre>
BIT #const
BIT addr
BIT dp
BIT addr, X
BIT dp, X
</pre>

==== Cycle Penalties ====
* BIT takes an extra cycle when the accumulator is 16 bits wide, in all [[addressing modes]]
* In [[direct page addressing]] modes (opcodes 24 and 34), BIT takes an extra cycle when the low byte of the [[direct page register]] is nonzero
* In [[Absolute Indexed, X Addressing]] only, BIT takes an extra cycle when adding the index crosses a [[page]] boundary

=== See Also ===
* [[AND]]
* [[BPL]]
* [[BNE]]
* [[BCC]]
* [[BCS]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/431 page 431] on BIT
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n131 page 121] on BIT
* 4.2.2.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n62 page 47] on BIT
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n262 page 249] on BIT
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n94 page 3-45] on BIT
* snes9x implementation of BIT: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L265
* undisbeliever on BIT: https://undisbeliever.net/snesdev/65816-opcodes.html#bit-test-memory-bits-against-accumulator
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BIT
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.2

[[Category:ASM]]
[[Category:Group Three Instructions]]
[[Category:Inherited from 6502]]

SBC

2026-05-15T02:53:35Z

Xetheria: /* Cycle Penalties */ page 533 does not have this superscript

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|E9
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|ED
|3 bytes
|4 cycles*
|+
|[[Absolute Long Addressing|Absolute Long]]
|EF
|4 bytes
|5 cycles*
|+
|[[Direct Page|Direct Page]]
|E5
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect Addressing|Direct Page Indirect]]
|F2
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|E7
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|FD
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|FF
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|F9
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|F5
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|E1
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|F1
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|F7
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|E3
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|F3
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|N
|V
|.
|.
|.
|.
|Z
|C
|}

'''SBC''' (Subtract with Carry/Borrow) is the main 65x subtraction instruction. The [[accumulator]] serves as both the minuend and where the difference is stored. The operand serves as the subtrahend. For example, SBC #6 does "a minus 6" but there is this caveat about the carry flag:

If the [[carry flag]] (aka borrow flag) is clear, one more is subtracted. As there is no subtract-without-carry instruction, [[SEC]] should be run beforehand or the carry flag should otherwise be ensured to be set, otherwise the difference may be one greater than expected.

The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

If the difference is negative, the carry flag will be cleared, otherwise it will be set. If the [[decimal flag]] is set, then [[binary coded decimal]] subtraction is performed, otherwise binary subtraction.

==== Syntax ====
<pre>
SBC #const
SBC addr
SBC long
SBC dp
SBC (dp)
SBC [dp]
SBC addr, X
SBC long, X
SBC addr, Y
SBC dp, X
SBC (dp, X)
SBC (dp), Y
SBC [dp], Y
SBC sr, S
SBC (sr, S), Y
</pre>

If you only need to subtract one, consider [[DEC]] instead.

==== Cycle Penalties ====
SBC takes an extra cycle for each of the following:
* if the accumulator is 16 bits wide, in all addressing modes
* when utilizing the [[direct register]] (opcodes E5, F2, E7, F5, E1, F1, and F7), if the low byte of the direct register is nonzero
* In both [[Absolute Indexed]] and [[Direct Page Indirect Indexed by Y]] addressing modes if adding an index crosses a [[page]] boundary

Unlike the 65c02, the 65c816 does not have a cycle penalty when subtracting in decimal mode.

In [[Eyes & Lichty]] on page 498, opcode F5 has a "0" superscript typo on the # of cycles column. On page 533 opcode F5 does not have this superscript.

=== See Also ===
* [[ADC]]
* [[SBC (SPC700)]]
* [[SUB (Super FX)]]
* [[DEX]]
* [[DEY]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] on SBC
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n189 page 179] on SBC
* 2.2.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n29 page 14] on SBC
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n284 page 271] on SBC
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n140 page 3-91] on SBC
* snes9x implementation of SBC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1133
* undisbeliever on SBC: https://undisbeliever.net/snesdev/65816-opcodes.html#sbc-subtract-with-borrow-from-accumulator
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#SBC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.1

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]

AND

2026-05-15T02:50:57Z

Xetheria: /* Cycle Penalties */ page 528 does not have this superscript

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|29
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|2D
|3 bytes
|4 cycles*
|+
|[[Absolute Long]]
|2F
|4 bytes
|5 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|25
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect]]
|32
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|27
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|3D
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|3F
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|39
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|35
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|21
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|31
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|37
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|23
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|33
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''AND''' is a 65x instruction that performs a logical AND. The conjunction is stored in the [[accumulator]]. The size of the accumulator determines how much data is ANDed: if 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

==== Syntax ====

<pre>
AND #const
AND addr
AND long
AND dp
AND (dp)
AND [dp]
AND addr, X
AND long, X
AND addr, Y
AND dp, X
AND (dp, X)
AND (dp), Y
AND [dp], Y
AND sr, S
AND (sr, S), Y
</pre>

==== Cycle Penalties ====
* In all [[addressing modes]], AND takes one extra cycle when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes only (opcodes 25, 32, 27, 35, 21, 31, 37), AND takes an extra cycle if the low byte of the [[direct page register]] is nonzero.
* In both [[Absolute Indexed]] addressing modes and [[Direct Page Indirect Indexed by Y]] admodes, AND takes an extra cycle if adding the index crosses a page boundary.

[[Eyes & Lichty]] has a typo on page 426, referring to cycle penalty #0 in a superscript for opcode 37. On page 528 opcode 37 does not have this superscript.

=== See Also ===
* [[ORA]]
* [[EOR]]
* [[BIT]]
* [[AND (SPC700)]]
* [[AND (Super FX)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/425 page 425] on AND
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n126 page 116] on AND
* 2.2.4.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n35 page 20] on AND
* [https://archive.org/details/mos_microcomputers_programming_manual/page/n204 B-3], lbid.
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n259 page 246] on AND
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n89 page 3-40] on AND
* undisbeliever on AND: https://undisbeliever.net/snesdev/65816-opcodes.html#and-and-accumulator-with-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#AND
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.1

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]

MERGE (Super FX)

2026-05-14T21:40:45Z

Xetheria: added how flags are affected

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''ROM Speed'''
|'''RAM Speed'''
|'''Cache Speed'''
|+
|[[Implied]] (type 1)
|70
|1 byte
|3 cycles
|3 cycles
|1 cycle
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[B Flag|B]]
|[[ALT1]]
|[[ALT2]]
|[[O/V]]
|[[Sign Flag|S]]
|[[CY]]
|[[Zero Flag|Z]]
|+
|0
|0
|0
|O/V
|S
|CY
|Z
|}

'''MERGE''' is a [[Super FX]] instruction that merges the high bytes of two specific general registers into the [[destination register]].

The high byte of Dreg comes from R7.
The low byte of Dreg comes from R8.

The official documentation has several bits labeled "B" not 'D" below the "Flags affected" table.[1] The O/V flag is set if the result of (D6, D7, D14, or D15) is 1 and cleared if 0. The sign flag is set if the result of (D7 or D15) is 1 and cleared if 0. The C/Y flag is set if the result of (D5, D6, D7, D13, D14, or D15) is 1 and cleared if 0. The zero flag is set if the result of (D4, D5, D6, D7, D12, D13, D14, or D15) is 1 and cleared if 0.

The [[ALT0]] state is restored.

The destination register should be specified in advance using [[WITH]] or [[TO]]. Otherwise, R0 serves as the default. The [[source register]] is ignored.

==== Syntax ====
<pre>
MERGE
</pre>

==== Example ====
Let:
Dreg : R9
R7 = 05aah
R8 = fc33h
After executing MERGE:
R9 = 05fch
and the sign, overflow, carry, and zero flags are set

[[File:gsu_merge.png]]

=== See Also ===
* [[HIB]]
* [[LOB]]
* [[SEX]]

=== External Links ===
* Official Nintendo documentation on MERGE: paragraph 9.56 on [https://archive.org/details/SNESDevManual/book2/page/n235 page 2-9-79 of Book II]
* example: [https://archive.org/details/SNESDevManual/book2/page/n236 page 2-9-80 of Book II], lbid.

[[Category:ASM]]
[[Category:Super FX]]
[[Category:Byte Transfer Instructions]]
[[Category:One-byte Instructions]]
[[Category:Expects Sreg/Dreg Prearranged]]

Background Mode

2026-05-14T09:13:30Z

Xetheria: pluralize bits

On the SNES hardware, the BG modes are used to specify the number of layers, the color depth of the graphics and some effect avaliable. There are 8 different BG modes. The BG mode is stored in bits 0,1 and 2 of $2105

* [[Mode 0]]: 4 layers, all using 2bpp graphic.
* [[Mode 1]]: 3 layers, two using 4bpp graphic and one using 2bpp graphic. This is one of the most commonly used video modes.
* [[Mode 2]]: 2 layers, both using 4bpp graphic. Each tile can be individually scrolled.
* [[Mode 3]]: 2 layers, one using 8bpp graphic and one using 4bpp graphic. The 8bpp layer can also directly specify colors from an 11-bit (RGB443) colorspace.
* [[Mode 4]]: 2 layers, one using the 8bpp graphic and one using 2bpp graphic. The 8bpp layer can directly specify colors as with Mode 3, and each tile can be individually scrolled as in Mode 2.
* [[Mode 5]]: 2 layers, one using 4bpp graphic and one using 2bpp graphic. In this mode, output is always 512 pixels horizontally with altered tile decoding to facilitate use of the 512-width and interlaced modes.
* [[Mode 6]]: 1 layer, using 4bpp graphic. Output is as in Mode 5, and individual tiles are scrolled as in Mode 2.
* [[Mode 7]]: 1 layer of 128x128 tiles from a set of 256, which can be interpreted as 8bpp or 7bpp (using the higher bit as a pixel priority bit) depending of bit 7 of $2133 . The layer may be rotated and scaled using matrix transformations. HDMA is often used to change the matrix parameters for each scanline to generate perspective effects, giving a pseudo-3d effect.

=== Reference ===
* [https://archive.org/details/SNESDevManual/book1/page/n62 page 2-3-1 of Book I] of the official Super Nintendo development manual

[[Category:SNES Hardware]]
[[Category:Video]]

fullsnes

2026-05-14T08:37:07Z

Xetheria: /* Errata */ BRK

'''Fullsnes''' is a large hardware reference for the SNES created by [[nocash]] with several ascii art illustrations.

=== Errata ===
* It may be more correct to say that the [[SPC700]] has no *hardware* interrupt sources rather than no interrupt sources whatsoever due to the existence of the [[BRK (SPC700)]] instruction.
* With regards to the [[break flag]], this sentence is dubious: "PHP opcodes always write "1" into the bit"
* The [[Color Math]] register at 2130h is missing an "S" - the full name is CGSWSEL not CGWSEL.
* In https://problemkaputt.de/fullsnes.htm#snesapumaincpucommunicationport, fullsnes only mentions storing the entrypoint to 2142h and does not mention whether the entrypoint is a word or byte (the other places in this section where the bracket notation omits "Byte" or "Word" it is a single byte being stored). The Official Super Nintendo development manual is clear that the program start address for the uploaded SPC700 driver is stored to both PORT 2 and 3 (as part of step 11 on page D-2).
* In https://problemkaputt.de/fullsnes.htm#snescartridgecicnotes, the formula for the [[Polynomial Counter]] is missing an inversion in the second term.
* In https://problemkaputt.de/fullsnes.htm#snespputimersandstatus, the [[Interlace Odd/Even Flag]] should use the term "field" instead of "frame" as an interlaced field is half of a frame
* In https://problemkaputt.de/fullsnes.htm#snesapuspc700ioports, it could be clearer that bits 0-3 of TnOUT are reset to 0 automatically by hardware after reading - it is not the programmer's responsibility to zero them after reading. [1]
* In https://problemkaputt.de/fullsnes.htm#snesapudspvolumeregisters, MVOL should stand for "main volume," not "master volume" because MVOL does not control the echo volume, and "Main Volume" is how the official docs expand "MVOL." [2]
* In https://problemkaputt.de/fullsnes.htm#snesapublockdiagram, the word "Reverb" is used (the only place this word is used in fullsnes) but should probably say "Echo" instead like the rest of the times this feature is mentioned, as they have slightly different musical meanings.
* In https://problemkaputt.de/fullsnes.htm#snesapudspechoregisters, "bit" should be plural in several places when describing the ESA buffer entry bytes
* In https://problemkaputt.de/fullsnes.htm#snescartridgeromimageinterleave, the worst case scenario can much worse than triple-interleaved or double-mis-de-interleaved - in fact ten interleavings of a normal 320Kbyte file is the identity operation, so in this particular case the worst is quintuple-interleaved.
* "Game Boy" is spelled several times as one word
* In the https://problemkaputt.de/fullsnes.htm#snesapumaincpucommunicationport notes there is a typo: "injumping"
* In https://problemkaputt.de/fullsnes.htm#snesapuspc700ioports under "SPC700 Waitstates on Internal Cycles" the note at the bottom has typo: "cylces"
* In the IPL Boot ROM Disassembly, both the zerofill and transfer loops have a typo where "loop" is spelled with one "o"
* The four communication ports between the [[APU]] and the [[5A22]] are prefixed CPUIO (cpu input/output) on the 5A22 side but APUI0 (apu eye zero) on the APU side

=== External Links ===

* https://problemkaputt.de/fullsnes.htm

=== References ===
# [https://archive.org/details/SNESDevManual/book1/page/n164 Page 3-5-2 of Book I] of the official Super Nintendo development manual: "When CN is read, the 4-bit up counter alone is cleared through IC internal timing"
# [https://archive.org/details/SNESDevManual/book1/page/n175 page 3-7-9 of Book I] lbid

[[Category:SNES Hardware]]
[[Category:Documents]]

Interrupt Handler

2026-05-14T07:05:00Z

Xetheria: numbered order

An '''Interrupt Handler''' is a subroutine which the CPU automatically runs when an interrupt occurs.

ISR stands for "interrupt service routine." Interrupts are never serviced when an instruction is only partially finished running (except if you count [[MVP]]/[[MVN]] which can be interrupted once every 7 cycles), but only after the instruction completes.

Use [[BRK]] to force a software interrupt.

When an interrupt occurs, the following are pushed to the [[stack]] in this exact order:
# [[program bank register]]
# [[program counter]] high byte
# program counter low byte
# [[status register]]

Return control back with [[RTI]] when on the [[65c816]] or [[RETI]] when on the [[SPC700]].

=== See Also ===
* [[NMI]]
* [[IRQ]]
* [[WAI]]
* [[Interrupt Request]]

[[Category:ASM]]

Program Counter

2026-05-14T06:36:43Z

Xetheria: linkify abs addressing

The '''Program Counter''' (PC) points to the next instruction byte to fetch. On both the [[65c816]] and [[S-SMP]] it is 16 bits wide. The low byte is called PCL and the high byte is called PCH.

If incremented past FFFFh, it wraps around to zero.[E&L, page 34] It is incremented after opcode fetch.

The 6502 had 16-bit [[absolute addressing]] but only an 8-bit adder, so in [[emulation mode]] branches that cross a page boundary incur a one cycle penalty. 65c816 native mode has no such penalty because the full 16-bit adder is used.

Interrupts cause the program counter to be pushed to the stack (high byte first).

The program counter alone is not enough to uniquely identify the current instruction - the [[program bank register]] holds the high byte of the full 24-bit address.

=== See Also ===
* [[Stack Pointer]]
* [[Super_FX#Program_Counter_(R15)]]
* [[BRA]]
* [[JMP]]
* [[RTS]]
* [[RTL]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/33 page 33]
* subparagraph 8.1.4 on [https://archive.org/details/SNESDevManual/book1/page/n182 page 3-8-4 of Book I] of the official Super Nintendo development manual
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#PC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.2.1.1

[[Category:ASM]]
[[Category:Registers]]
[[Category:Inherited from 6502]]

Program Counter

2026-05-14T06:26:22Z

Xetheria: explain pbr

The '''Program Counter''' (PC) points to the next instruction byte to fetch. On both the [[65c816]] and [[S-SMP]] it is 16 bits wide. The low byte is called PCL and the high byte is called PCH.

If incremented past FFFFh, it wraps around to zero.[E&L, page 34] It is incremented after opcode fetch.

The 6502 had 16-bit absolute addressing but only an 8-bit adder, so in [[emulation mode]] branches that cross a page boundary incur a one cycle penalty. 65c816 native mode has no such penalty because the full 16-bit adder is used.

Interrupts cause the program counter to be pushed to the stack (high byte first).

The program counter alone is not enough to uniquely identify the current instruction - the [[program bank register]] holds the high byte of the full 24-bit address.

=== See Also ===
* [[Stack Pointer]]
* [[Super_FX#Program_Counter_(R15)]]
* [[BRA]]
* [[JMP]]
* [[RTS]]
* [[RTL]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/33 page 33]
* subparagraph 8.1.4 on [https://archive.org/details/SNESDevManual/book1/page/n182 page 3-8-4 of Book I] of the official Super Nintendo development manual
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#PC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.2.1.1

[[Category:ASM]]
[[Category:Registers]]
[[Category:Inherited from 6502]]

Program Counter

2026-05-14T05:07:56Z

Xetheria: when incremented

The '''Program Counter''' (PC) points to the next instruction byte to fetch. On both the [[65c816]] and [[S-SMP]] it is 16 bits wide. The low byte is called PCL and the high byte is called PCH.

If incremented past FFFFh, it wraps around to zero.[E&L, page 34] It is incremented after opcode fetch.

The 6502 had 16-bit absolute addressing but only an 8-bit adder, so in [[emulation mode]] branches that cross a page boundary incur a one cycle penalty. 65c816 native mode has no such penalty because the full 16-bit adder is used.

Interrupts cause the program counter to be pushed to the stack (high byte first).

=== See Also ===
* [[Program Bank Register]]
* [[Stack Pointer]]
* [[Super_FX#Program_Counter_(R15)]]
* [[BRA]]
* [[JMP]]
* [[RTS]]
* [[RTL]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/33 page 33]
* subparagraph 8.1.4 on [https://archive.org/details/SNESDevManual/book1/page/n182 page 3-8-4 of Book I] of the official Super Nintendo development manual
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#PC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.2.1.1

[[Category:ASM]]
[[Category:Registers]]
[[Category:Inherited from 6502]]

Pipeline

2026-05-14T05:05:09Z

Xetheria: Xetheria moved page Pipeline to Pipelining

#REDIRECT [[Pipelining]]

Pipelining

2026-05-14T05:05:09Z

Xetheria: Xetheria moved page Pipeline to Pipelining

'''Pipelining''' is a feature of 65x processors to increase throughput.

When finishing up an [[ADC]] instruction for example, these two things are happening simultaneously:
* opcode fetch for the next instruction
* the [[internal cycle]] of putting the sum into the accumulator.

=== See Also ===
* [[Super_FX#Pipeline_Processing]]

=== Reference ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/40 page 40]

[[Category:SNES Hardware]]
[[Category:ASM]]

Index Register Select

2026-05-14T03:55:28Z

Xetheria: RTI pops it off the stack

'''Index Register Select''' (X) is a flag in the [[processor status register]] (bit 4) of the [[65c816]]. It indicates how wide the [[index register]]s are:

* When clear, both index registers are 16 bits wide. It can only be clear in [[native mode]].
* When set or in [[emulation mode]], both index registers are 8 bits wide and the high bytes are forced to zero.

It is not possible to control the width of the two index registers individually.

It can be affected by:

* [[REP]] (clears it if bit 4 of operand is set)
* [[SEP]] (sets it if bit 4 of operand is set)
* [[PLP]] (pops it off the [[stack]])
* [[RTI]] (pops it off the stack)

It affects the behavior of (possibly incomplete list):
* [[LDX]]
* [[LDY]]
* [[STX]]
* [[STY]]
* [[CPX]]
* [[CPY]]
* [[PHX]]
* [[PHY]]
* [[PLX]]
* [[PLY]]
* [[INX]]
* [[INY]]
* [[DEX]]
* [[DEY]]
* [[TXY]]
* [[TYX]]
* [[TXS]]
* [[TSX]]

In [[emulation mode]], the x flag becomes the [[break flag]].

There are no BXS or BXC instructions that examine this flag.

=== See Also ===
* [[Memory/Accumulator Select]]
* [[X Index Register]]
* [[Y Index Register]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422], Table 18.2. 65x Flags.
* 65c816 datasheet paragraph 2.7 "Index (X and Y)"

[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

Index Register Select

2026-05-14T03:02:07Z

Xetheria: /* References */ paragraph name

'''Index Register Select''' (X) is a flag in the [[processor status register]] (bit 4) of the [[65c816]]. It indicates how wide the [[index register]]s are:

* When clear, both index registers are 16 bits wide. It can only be clear in [[native mode]].
* When set or in [[emulation mode]], both index registers are 8 bits wide and the high bytes are forced to zero.

It is not possible to control the width of the two index registers individually.

It can be affected by:

* [[REP]] (clears it if bit 4 of operand is set)
* [[SEP]] (sets it if bit 4 of operand is set)
* [[PLP]] (pops it off the [[stack]])
* [[RTI]]

It affects the behavior of (possibly incomplete list):
* [[LDX]]
* [[LDY]]
* [[STX]]
* [[STY]]
* [[CPX]]
* [[CPY]]
* [[PHX]]
* [[PHY]]
* [[PLX]]
* [[PLY]]
* [[INX]]
* [[INY]]
* [[DEX]]
* [[DEY]]
* [[TXY]]
* [[TYX]]
* [[TXS]]
* [[TSX]]

In [[emulation mode]], the x flag becomes the [[break flag]].

There are no BXS or BXC instructions that examine this flag.

=== See Also ===
* [[Memory/Accumulator Select]]
* [[X Index Register]]
* [[Y Index Register]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422], Table 18.2. 65x Flags.
* 65c816 datasheet paragraph 2.7 "Index (X and Y)"

[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

BRA (Super FX)

2026-05-13T21:53:43Z

Xetheria: all flags ignored

BRA (Super FX)

2026-05-13T21:11:39Z

Xetheria: /* See Also */ (BRA spc700)

Timing Control Unit

2026-05-13T21:10:30Z

Xetheria: /* List of instructions without cycle penalties: */ BRA+JMP

The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.

==== List of instructions with cycle penalties: ====

* [[ADC]]
* [[AND]]
* [[ASL]]
* [[BCC]]
* [[BCS]]
* [[BEQ]]
* [[BIT]]
* [[BMI]]
* [[BNE]]
* [[BPL]]
* [[BRA]]
* [[BRK]]
* [[BVC]]
* [[BVS]]
* [[CMP]]
* [[COP]]
* [[CPX]]
* [[CPY]]
* [[DEC]]
* [[EOR]]
* [[INC]]
* [[LDA]]
* [[LDX]]
* [[LDY]]
* [[LSR]]
* [[ORA]]
* [[PEI]]
* [[PHA]]
* [[PHX]]
* [[PHY]]
* [[PLA]]
* [[PLX]]
* [[PLY]]
* [[ROL]]
* [[ROR]]
* [[RTI]]
* [[SBC]]
* [[STA]]
* [[STX]]
* [[STY]]
* [[STZ]]
* [[TRB]]
* [[TSB]]
* and most [[SPC700]] branching commands

==== List of instructions without cycle penalties: ====

* [[BRL]]
* [[CLC]]
* [[CLD]]
* [[CLI]]
* [[CLV]]
* [[DEX]]
* [[DEY]]
* [[INX]]
* [[INY]]
* [[JMP]] / JML
* [[JSL]]
* [[JSR]]
* [[MVN]]
* [[MVP]]
* [[NOP]]
* [[PEA]]
* [[PER]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]]
* [[PLB]]
* [[PLD]]
* [[PLP]]
* [[REP]]
* [[RTL]]
* [[RTS]]
* [[SEC]]
* [[SED]]
* [[SEI]]
* [[SEP]]
* [[STP]]
* [[TAX]]
* [[TAY]]
* [[TCD]]
* [[TCS]]
* [[TDC]]
* [[TSC]]
* [[TSX]]
* [[TXA]]
* [[TXS]]
* [[TXY]]
* [[TYA]]
* [[TYX]]
* [[WAI]]
* [[WDM]]
* [[XBA]]
* [[XCE]]
* All non-branching [[SPC700]] instructions
* [[BRA (SPC700)]]
* [[JMP (SPC700)]]

=== Reference ===
* section 2.2 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:SNES Hardware]]
[[Category:Inherited from 6502]]
[[Category:Timing]]

BRA

2026-05-13T21:08:52Z

Xetheria: /* See Also */ spc700

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Program Counter Relative]]
|80
|2 bytes
|3 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|.
|.
|.
|.
|.
|.
|.
|.
|}

'''BRA''' (BRanch Always) is a [[65c816]] instruction that performs an unconditional jump. The signed displacement ranges from -128 to 127. The displacement is sign-extended to 16 bits and added to the [[program counter]]. The displacement is measured from the instruction following BRA.

BRA is relocatable. No flags are affected.

==== Syntax ====
<pre>
BRA nearlabel
</pre>

BRA has the same timing as other branches, it just has no "branch not taken" case.

===== Cycle Penalty =====
* BRA takes one additional cycle if the branch crosses a page boundary in [[emulation mode]].

=== See Also ===
* [[JMP]]
* [[BRA (Super FX)]]
* [[BRA (SPC700)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/435 page 435] on BRA
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n135 page 125] on BRA
* snes9x implementation of BRA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1390
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.2.1.1

[[Category:ASM]]
[[Category:65c02 additions]]
[[Category:Unconditional Branches]]
[[Category:Two-byte Instructions]]
[[Category:Relocatable Instructions]]
[[Category:Single Admode Mnemonics]]

Timing Control Unit

2026-05-13T16:34:46Z

Xetheria: /* List of instructions without cycle penalties: */ spc700

The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.

==== List of instructions with cycle penalties: ====

* [[ADC]]
* [[AND]]
* [[ASL]]
* [[BCC]]
* [[BCS]]
* [[BEQ]]
* [[BIT]]
* [[BMI]]
* [[BNE]]
* [[BPL]]
* [[BRA]]
* [[BRK]]
* [[BVC]]
* [[BVS]]
* [[CMP]]
* [[COP]]
* [[CPX]]
* [[CPY]]
* [[DEC]]
* [[EOR]]
* [[INC]]
* [[LDA]]
* [[LDX]]
* [[LDY]]
* [[LSR]]
* [[ORA]]
* [[PEI]]
* [[PHA]]
* [[PHX]]
* [[PHY]]
* [[PLA]]
* [[PLX]]
* [[PLY]]
* [[ROL]]
* [[ROR]]
* [[RTI]]
* [[SBC]]
* [[STA]]
* [[STX]]
* [[STY]]
* [[STZ]]
* [[TRB]]
* [[TSB]]
* and most [[SPC700]] branching commands

==== List of instructions without cycle penalties: ====

* [[BRL]]
* [[CLC]]
* [[CLD]]
* [[CLI]]
* [[CLV]]
* [[DEX]]
* [[DEY]]
* [[INX]]
* [[INY]]
* [[JMP]] / JML
* [[JSL]]
* [[JSR]]
* [[MVN]]
* [[MVP]]
* [[NOP]]
* [[PEA]]
* [[PER]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]]
* [[PLB]]
* [[PLD]]
* [[PLP]]
* [[REP]]
* [[RTL]]
* [[RTS]]
* [[SEC]]
* [[SED]]
* [[SEI]]
* [[SEP]]
* [[STP]]
* [[TAX]]
* [[TAY]]
* [[TCD]]
* [[TCS]]
* [[TDC]]
* [[TSC]]
* [[TSX]]
* [[TXA]]
* [[TXS]]
* [[TXY]]
* [[TYA]]
* [[TYX]]
* [[WAI]]
* [[WDM]]
* [[XBA]]
* [[XCE]]
* All non-branching [[SPC700]] instructions

=== Reference ===
* section 2.2 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:SNES Hardware]]
[[Category:Inherited from 6502]]
[[Category:Timing]]

Timing Control Unit

2026-05-13T08:01:34Z

Xetheria: /* List of instructions with cycle penalties: */ spc700

The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.

==== List of instructions with cycle penalties: ====

* [[ADC]]
* [[AND]]
* [[ASL]]
* [[BCC]]
* [[BCS]]
* [[BEQ]]
* [[BIT]]
* [[BMI]]
* [[BNE]]
* [[BPL]]
* [[BRA]]
* [[BRK]]
* [[BVC]]
* [[BVS]]
* [[CMP]]
* [[COP]]
* [[CPX]]
* [[CPY]]
* [[DEC]]
* [[EOR]]
* [[INC]]
* [[LDA]]
* [[LDX]]
* [[LDY]]
* [[LSR]]
* [[ORA]]
* [[PEI]]
* [[PHA]]
* [[PHX]]
* [[PHY]]
* [[PLA]]
* [[PLX]]
* [[PLY]]
* [[ROL]]
* [[ROR]]
* [[RTI]]
* [[SBC]]
* [[STA]]
* [[STX]]
* [[STY]]
* [[STZ]]
* [[TRB]]
* [[TSB]]
* and most [[SPC700]] branching commands

==== List of instructions without cycle penalties: ====

* [[BRL]]
* [[CLC]]
* [[CLD]]
* [[CLI]]
* [[CLV]]
* [[DEX]]
* [[DEY]]
* [[INX]]
* [[INY]]
* [[JMP]] / JML
* [[JSL]]
* [[JSR]]
* [[MVN]]
* [[MVP]]
* [[NOP]]
* [[PEA]]
* [[PER]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]]
* [[PLB]]
* [[PLD]]
* [[PLP]]
* [[REP]]
* [[RTL]]
* [[RTS]]
* [[SEC]]
* [[SED]]
* [[SEI]]
* [[SEP]]
* [[STP]]
* [[TAX]]
* [[TAY]]
* [[TCD]]
* [[TCS]]
* [[TDC]]
* [[TSC]]
* [[TSX]]
* [[TXA]]
* [[TXS]]
* [[TXY]]
* [[TYA]]
* [[TYX]]
* [[WAI]]
* [[WDM]]
* [[XBA]]
* [[XCE]]

=== Reference ===
* section 2.2 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:SNES Hardware]]
[[Category:Inherited from 6502]]
[[Category:Timing]]

Two-Phase Access

2026-05-13T07:57:48Z

Xetheria: SA-1 category

'''Two-Phase Access''' is when both the [[SA-1]] and [[5A22]] access the ROM.

=== Reference ===
* Figure 2.2.1.3 on [https://archive.org/details/SNESDevManual/book2/page/n14 page 1-2-3 of Book II] of the official Super Nintendo development manual

[[Category:Official Jargon]]
[[Category:SA-1]]

Two-Phase Access

2026-05-13T07:56:44Z

Xetheria: better description

Direct Page Register

2026-05-13T05:32:30Z

Xetheria: or simply Direct Register

The '''Direct Page Register''' (or simply the '''Direct Register''') exists on the [[65c816]] and is 16 bits wide.[1] It holds current the location of the [[direct page]]. The low byte is called DL and the high byte DH.

The direct page register is cleared to point to the [[zero page]] on reset.[2]

[[File:dp.png]]

Its value can be pushed to the [[stack]] with [[PHD]] and pulled off the stack with [[PLD]].

Its value can be transferred to and from the full 16 bit [[accumulator]] with [[TCD]] and [[TDC]].

=== References ===
# page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.6 on page 7, lbid.
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53]

[[Category:ASM]]
[[Category:Registers]]
[[Category:65c816 additions]]

List of Anomie's Docs

2026-05-13T04:10:14Z

Xetheria: /* Errata */ added at any point in the opcode

There are nine documents by anomie available on [[RHDN]]:

* [https://www.romhacking.net/documents/193 SNES Memory Mapping]
* [https://www.romhacking.net/documents/196 Register]
* [https://www.romhacking.net/documents/199 SNES Timing]
* [https://www.romhacking.net/documents/197 SPC700 with boot rom disassembly]
* [https://www.romhacking.net/documents/198 SPC700 Cycles]
* [https://www.romhacking.net/documents/191 S-DSP]
* [https://www.romhacking.net/documents/194 SNES OpenBus and Wrapping]
* [https://www.romhacking.net/documents/195 SNES Port]
* [https://www.romhacking.net/documents/192 C4 chip]

=== Errata ===
* In '''regs.txt''' under "BG Modes" we have "The SNES has 7 [[background modes]]," it should say 8.
* In the S-DSP doc, we have "Certain games do seem to depend on these exact formulas, trying to '''simplify''' will break some sound effects." But "approximate" would probably be clearer than "simplify," as in mathematics simplifying a formula only reduces the number of symbols used to express it, which may be easier to read but otherwise leaves it equivalent.
* In '''ob-wrap.txt''', the first result is that [[Program Counter]] Increment "Always wraps within the [[bank]], at any point in the opcode." But as opcodes are merely the first byte of an instruction, this result would probably be clearer if the last word were "instruction."

=== See Also ===
* [[List of Y0shi's Docs]]

[[Category:SNES Hardware]]
[[Category:Documents]]
[[Category:Lists]]

S-SMP

2026-05-12T23:29:51Z

Xetheria: linkify zp

The '''S-SMP''' is a Sony SPC700 series 8-bit 65x-based MPU which serves as the SNES' sound chip. It talks to the [[Ricoh 5A22]] over four ports via the [[SNES Bus]] and [[CPU Data Bus]]. It is clocked by [[CPUK]]. The minimum command execution time is 1.953 microseconds.[2]

The following registers are 8-bit:
* [[Accumulator]]
* [[X Index Register]]
* [[Y Index Register]]
* [[Program Status Word]]
* [[Stack Pointer]]

The following registers are 16-bit:
* [[Program Counter]]
* [[YA]] (which is virtually just the Y index reg concatenated to A)

Instructions that try to access memory straddling past the end of [[ARAM]] (the last byte of which is at $FFFF) will wrap around and end up accessing the [[zeropage]] (which is at $0000). Accesses that use [[direct page addressing]] will wrap within the [[direct page]].

The stack is always located in page one (at $0100). Memory accesses that straddle the end of the stack will wrap to the beginning of the stack.

Operands that use [[absolute addressing]] are prefixed with an exclamation point (!).

The S-SMP has no hardware interrupt sources, but it does have [[BRK (SPC700)|BRK]].

=== See Also ===
* [[SPC700 Opcode Matrix]]

=== References ===
# [https://www.romhacking.net/documents/197 anomie's SPC700 doc]
# SNES Sound Source Outline on [https://archive.org/details/SNESDevManual/book1/page/n152 page 3-1-1 of Book I] of the official Super Nintendo development manual
# subparagraph 22.5.1 on [https://archive.org/details/SNESDevManual/book1/page/n97 page 2-22-1 of Book I], lbid.

[[Category:SNES Hardware]]
[[Category:ICs with unconnected pins]]
[[Category:Integrated Circuits]]
[[Category:Audio]]
[[Category:SPC700]]

Direct Page Register

2026-05-12T02:12:27Z

Xetheria: It -> its value

The '''Direct Page Register''' exists on the [[65c816]] and is 16 bits wide.[1] It holds current the location of the [[direct page]]. The low byte is called DL and the high byte DH.

The direct page register is cleared to point to the [[zero page]] on reset.[2]

[[File:dp.png]]

Its value can be pushed to the [[stack]] with [[PHD]] and pulled off the stack with [[PLD]].

Its value can be transferred to and from the full 16 bit [[accumulator]] with [[TCD]] and [[TDC]].

=== References ===
# page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.6 on page 7, lbid.
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53]

[[Category:ASM]]
[[Category:Registers]]
[[Category:65c816 additions]]

Direct Page Register

2026-05-11T23:09:08Z

Xetheria: DL and DH

The '''Direct Page Register''' exists on the [[65c816]] and is 16 bits wide.[1] It holds current the location of the [[direct page]]. The low byte is called DL and the high byte DH.

The direct page register is cleared to point to the [[zero page]] on reset.[2]

[[File:dp.png]]

Its value can be pushed to the [[stack]] with [[PHD]] and pulled off the stack with [[PLD]].

It can be transferred to and from the full 16 bit [[accumulator]] with [[TCD]] and [[TDC]].

=== References ===
# page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.6 on page 7, lbid.
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53]

[[Category:ASM]]
[[Category:Registers]]
[[Category:65c816 additions]]

DL

2026-05-11T23:07:30Z

Xetheria: consolidate redirect

#redirect [[Direct Page Register]]

DH

2026-05-11T23:06:59Z

Xetheria: consolidate redirect

#redirect [[Direct Page Register]]

SBC

2026-05-11T15:13:42Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|E9
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|ED
|3 bytes
|4 cycles*
|+
|[[Absolute Long Addressing|Absolute Long]]
|EF
|4 bytes
|5 cycles*
|+
|[[Direct Page|Direct Page]]
|E5
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect Addressing|Direct Page Indirect]]
|F2
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|E7
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|FD
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|FF
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|F9
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|F5
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|E1
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|F1
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|F7
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|E3
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|F3
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|N
|V
|.
|.
|.
|.
|Z
|C
|}

'''SBC''' (Subtract with Carry/Borrow) is the main 65x subtraction instruction. The [[accumulator]] serves as both the minuend and where the difference is stored. The operand serves as the subtrahend. For example, SBC #6 does "a minus 6" but there is this caveat about the carry flag:

If the [[carry flag]] (aka borrow flag) is clear, one more is subtracted. As there is no subtract-without-carry instruction, [[SEC]] should be run beforehand or the carry flag should otherwise be ensured to be set, otherwise the difference may be one greater than expected.

The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

If the difference is negative, the carry flag will be cleared, otherwise it will be set. If the [[decimal flag]] is set, then [[binary coded decimal]] subtraction is performed, otherwise binary subtraction.

==== Syntax ====
<pre>
SBC #const
SBC addr
SBC long
SBC dp
SBC (dp)
SBC [dp]
SBC addr, X
SBC long, X
SBC addr, Y
SBC dp, X
SBC (dp, X)
SBC (dp), Y
SBC [dp], Y
SBC sr, S
SBC (sr, S), Y
</pre>

If you only need to subtract one, consider [[DEC]] instead.

==== Cycle Penalties ====
SBC takes an extra cycle for each of the following:
* if the accumulator is 16 bits wide, in all addressing modes
* when utilizing the [[direct register]] (opcodes E5, F2, E7, F5, E1, F1, and F7), if the low byte of the direct register is nonzero
* In both [[Absolute Indexed]] and [[Direct Page Indirect Indexed by Y]] addressing modes if adding an index crosses a [[page]] boundary

Unlike the 65c02, the 65c816 does not have a cycle penalty when subtracting in decimal mode.

In [[Eyes & Lichty]] on page 498, opcode F5 has a "0" superscript typo on the # of cycles column.

=== See Also ===
* [[ADC]]
* [[SBC (SPC700)]]
* [[SUB (Super FX)]]
* [[DEX]]
* [[DEY]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] on SBC
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n189 page 179] on SBC
* 2.2.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n29 page 14] on SBC
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n284 page 271] on SBC
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n140 page 3-91] on SBC
* snes9x implementation of SBC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1133
* undisbeliever on SBC: https://undisbeliever.net/snesdev/65816-opcodes.html#sbc-subtract-with-borrow-from-accumulator
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#SBC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.1

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]

ORA

2026-05-11T15:06:52Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|09
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|0D
|3 bytes
|4 cycles*
|+
|[[Absolute Long Addressing|Absolute Long]]
|0F
|4 bytes
|5 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|05
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect]]
|12
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|07
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|1D
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|1F
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|19
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|15
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|01
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|11
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|17
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|03
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|13
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''ORA''' is a 65x instruction that performs a logical OR between the datum at the effective address and the [[accumulator]] and stores the disjunction in the accumulator. The size of the accumulator determines whether 8 or 16 bits are ORed together with it. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

==== Syntax ====
<pre>
ORA #const
ORA addr
ORA long
ORA dp
ORA (dp)
ORA [dp]
ORA addr, X
ORA long, X
ORA addr, Y
ORA dp, X
ORA (dp, X)
ORA (dp), Y
ORA [dp], Y
ORA sr, S
ORA (sr, S), Y
</pre>

==== Cycle Penalties ====
* In all [[addressing modes]], ORA takes one extra cycle when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes (opcodes 05, 12, 07, 15, 01, 11, and 17), ORA takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
* Both [[Absolute Indexed]] and [[Direct Page Indirect Indexed by Y]] addressing modes have another cycle penalty when indexing crosses a page boundary

=== See Also ===
* [[AND]]
* [[EOR]]
* [[OR (Super FX)]]
* [[XOR (Super FX)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/471 page 471] on ORA
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n166 page 156] on ORA
* 2.2.4.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n36 page 21] on ORA
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n279 page 266] on ORA
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n128 page 3-79] on ORA
* snes9x implementation of ORA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L917
* undisbeliever on ORA: https://undisbeliever.net/snesdev/65816-opcodes.html#ora-or-accumulator-with-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#ORA
* Bruce, Clark. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.1

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]

LSR

2026-05-11T15:02:58Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Accumulator Addressing|Accumulator]]
|4A
|1 byte
|2 cycles
|+
|[[Absolute]]
|4E
|3 bytes
|6 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|46
|2 bytes
|5 cycles*
|+
|[[Absolute Indexed by X]]
|5E
|3 bytes
|7 cycles*
|+
|[[Direct Page Indexed by X]]
|56
|2 bytes
|6 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|0
|.
|.
|.
|.
|.
|Z
|C
|}

'''LSR''' (Logical Shift Right) is a 65x instruction that shifts every bit of a value one bit to the right (division by two). The most significant bit and [[negative flag]] are cleared. The least significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROR]]).

The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

==== Syntax ====
<pre>
LSR
LSR A
LSR addr
LSR dp
LSR addr, X
LSR dp, X
</pre>

==== Cycle Penalties ====
* Except in [[accumulator addressing]], LSR takes an extra two cycles when the accumulator is 16 bits wide
* In [[direct page addressing]] modes (opcodes 46 and 56), LSR takes another extra cycle if the low byte of the [[direct page register]] is nonzero.

[[File:816_lsr.png]]

=== See Also ===
* [[ASL]]
* [[LSR (SPC700)]]
* [[LSR (Super FX)]]
* [[DIV2]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/465 page 465] on LSR
* lbid [https://archive.org/details/0893037893ProgrammingThe65816/page/191 page 191], before & after diagram of LSR
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n162 page 152] on LSR
* 10.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n169 page 148] on LSR
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n278 page 265] on LSR
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n125 page 3-76] on LSR
* snes9x implementation of LSR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L862
* undisbeliever on LSR: https://undisbeliever.net/snesdev/65816-opcodes.html#lsr-logical-shift-right
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LSR
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.3

[[Category:ASM]]
[[Category:Group Two Instructions]]
[[Category:Read-Modify-Write Instructions]]
[[Category:Inherited from 6502]]

LDY

2026-05-11T15:01:56Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|A0
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|AC
|3 bytes
|4 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|A4
|2 bytes
|3 cycles*
|+
|[[Absolute Indexed by X]]
|BC
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|B4
|2 bytes
|4 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''LDY''' (Load Y) is a 65x instruction that loads a value into the [[Y index register]]. The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is loaded from the effective address and the high-order byte from the effective address plus one.

In [[immediate addressing]] only, LDY takes a total of 3 bytes when the index registers are 16 bits wide.

==== Syntax ====
<pre>
LDY #const
LDY addr
LDY dp
LDY addr, X
LDY dp, X
</pre>

==== Cycle Penalties ====
* In all [[addressing mode]]s, LDY takes an extra cycle when the index registers are 16 bits wide
* In [[direct page addressing]] modes (opcodes A4 and B4), LDY takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
* In [[Absolute Indexed, Y Addressing]] only, LDY takes an another extra cycle if adding the index crosses a page boundary

=== See Also ===
* [[STY]]
* [[LDA]]
* [[LDX]]
* [[TAY]]
* [[TXY]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/n490 page 464] on LDY
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n161 page 151] on LDY
* 7.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n114 page 96] on LDY
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n277 page 264] on LDY
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n123 page 3-74] on LDY
* snes9x implementation of LDY: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L817
* undisbeliever on LDY: https://undisbeliever.net/snesdev/65816-opcodes.html#ldy-load-index-register-y-from-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LDY

[[Category:ASM]]
[[Category:Group Three Instructions]]
[[Category:Inherited from 6502]]
[[Category:Load/Store Instructions]]

LDX

2026-05-11T15:00:25Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|A2
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|AE
|3 bytes
|4 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|A6
|2 bytes
|3 cycles*
|+
|[[Absolute Indexed by Y]]
|BE
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by Y]]
|B6
|2 bytes
|4 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''LDX''' (Load X) is a 65x instruction that loads a value into the [[X index register]]. The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is loaded from the effective address and the high-order byte from the effective address plus one.

In [[immediate addressing]] only, LDX is a total of 3 bytes long when the index registers are 16 bits wide.

==== Syntax ====
<pre>
LDX #const
LDX addr
LDX dp
LDX addr, Y
LDX dp, Y
</pre>

==== Cycle Penalties ====
* In all [[addressing mode]]s, LDX takes an extra cycle when the index registers are 16 bits wide
* In [[direct page addressing]] modes (opcodes A6 and B6), LDX takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
* In [[Absolute Indexed, Y Addressing]] only, LDX takes an another extra cycle if adding the index crosses a page boundary

=== See Also ===
* [[STX]]
* [[LDA]]
* [[LDY]]
* [[TAX]]
* [[TYX]]
* [[TSX]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/463 page 463] on LDX
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n160 page 150] on LDX
* 7.0 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n114 page 96] on LDX
* [https://archive.org/details/mos_microcomputers_programming_manual/page/n219 B-18], lbid.
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n277 page 264] on LDX
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n121 page 3-72] on LDX
* snes9x implementation of LDX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L772
* undisbeliever on LDX: https://undisbeliever.net/snesdev/65816-opcodes.html#ldx-load-index-register-x-from-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LDX

[[Category:ASM]]
[[Category:Group Two Instructions]]
[[Category:Inherited from 6502]]
[[Category:Load/Store Instructions]]

LDA

2026-05-11T14:59:05Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|A9
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|AD
|3 bytes
|4 cycles*
|+
|[[Absolute Long]]
|AF
|4 bytes
|5 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|A5
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect]]
|B2
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|A7
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|BD
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|BF
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|B9
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|B5
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|A1
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|B1
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|B7
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|A3
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|B3
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''LDA''' (LoaD Accumulator) is a 65x instruction that loads a value into the accumulator. The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is loaded from the effective address and the high-order byte from the effective address plus one.

In [[immediate addressing]] only, LDA is a total of 3 bytes long when the accumulator is 16 bits wide.

==== Syntax ====
<pre>
LDA #const
LDA addr
LDA long
LDA dp
LDA (dp)
LDA [dp]
LDA addr, X
LDA long, X
LDA addr, Y
LDA dp, X
LDA (dp, X)
LDA (dp), Y
LDA [dp], Y
LDA sr, S
LDA (sr, S), Y
</pre>

If you want to load zero into the [[accumulator]], [[TDC]] may be a better choice, but only if the [[direct page register]] is zero.

==== Cycle Penalties ====
* In all [[addressing modes]], LDA takes one extra cycle when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes (opcodes A5, B2, A7, B5, A1, B1, and B7), LDA takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
* In both the [[Absolute Indexed]] and the [[Direct Page Indirect Indexed by Y]] admodes, LDA takes an extra cycle if adding the index crosses a page boundary.

=== See Also ===
* [[STA]]
* [[LDX]]
* [[LDY]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/462 page 462] on LDA
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n159 page 149] on LDA
* 2.1.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n19 page 4] on LDA
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n276 page 263] on LDA
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n120 page 3-71] on LDA
* snes9x implementation of LDA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L678
* undisbeliever on LDA: https://undisbeliever.net/snesdev/65816-opcodes.html#lda-load-accumulator-from-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#LDA

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]
[[Category:Load/Store Instructions]]

INC

2026-05-11T14:55:50Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Accumulator Addressing | Accumulator]]
|1A
|1 byte
|2 cycles
|+
|[[Absolute Addressing | Absolute]]
|EE
|3 bytes
|6 cycles*
|+
|[[Direct Page Addressing | Direct Page]]
|E6
|2 bytes
|5 cycles*
|+
|[[Absolute Indexed by X]]
|FE
|3 bytes
|7 cycles*
|+
|[[Direct Page Indexed by X]]
|F6
|2 bytes
|6 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''INC''' (Increment) is a 65x instruction that increments the value in the location specified by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low byte is located at the effective address and the high byte at the effective address plus one. An alternate mnemonic when the operand is the accumulator is "INA."

INC ignores the [[decimal mode flag]] and the [[carry flag]].

==== Syntax ====
<pre>
INC
INC A
INA
INC addr
INC dp
INC addr, X
INC dp, X
</pre>

To test for wraparound, examine the [[zero flag]]. If you need to add two or more to the [[accumulator]], consider [[ADC]] instead of INC.

==== Cycle Penalties ====
* Except in [[accumulator addressing]], INC takes two extra cycles when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes (opcodes E6 and F6), INC takes an extra cycle if the low byte of the [[direct page register]] is nonzero.

Although the NMOS 6502 does have INC, it does not work on the accumulator. The NES CPU is one such system that lacks that addressing mode for INC. When porting code to the 65c816, utilizing INC more often instead of ADC can make code smaller and faster.

=== See Also ===
* [[INX]]
* [[INY]]
* [[DEC]]
* [[INC (SPC700)]]
* [[INC (Super FX)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/456 page 456] on INC
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n152 page 142] on INC
* 10.7 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n176 page 155] on INC
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n273 page 260] on INC
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n114 page 3-65] on INC
* snes9x implementation of INC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L627
* undisbeliever on INC: https://undisbeliever.net/snesdev/65816-opcodes.html#inc-increment
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#INC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.3

[[Category:ASM]]
[[Category:Group Two Instructions]]
[[Category:Read-Modify-Write Instructions]]
[[Category:Inherited from 6502]]

Direct Page Indirect Indexed, Y

2026-05-11T14:54:37Z

Xetheria: created page

#redirect [[Direct Page Indirect Indexed, Y Addressing]]

EOR

2026-05-11T14:53:43Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|49
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|4D
|3 bytes
|4 cycles*
|+
|[[Absolute Long Addressing|Absolute Long]]
|4F
|4 bytes
|5 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|45
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect]]
|52
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|47
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|5D
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|5F
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|59
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|55
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|41
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|51
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|57
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|43
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|53
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''EOR''' is a 65x instruction that performs a bitwise [https://mathworld.wolfram.com/XOR.html exclusive or] between its operand and the accumulator. The sum is stored in the [[accumulator]]. The size of the accumulator determines whether 8 or 16 bits are EORed together with it. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

==== Syntax ====
<pre>
EOR #const
EOR addr
EOR long
EOR dp
EOR (dp)
EOR [dp]
EOR addr, X
EOR long, X
EOR addr, Y
EOR dp, X
EOR (dp, X)
EOR (dp), Y
EOR [dp], Y
EOR sr, S
EOR (sr, S), Y
</pre>

One example usage of EOR is to flip all the bits of the accumulator:[10]

<pre>
EOR #$FFFF
</pre>

==== Cycle Penalties ====
* In all [[addressing modes]], EOR takes one extra cycle when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes (opcodes 45, 52, 47, 55, 41, 51, and 57), EOR takes one additional cycle if the low byte of the [[direct page register]] is nonzero.
* In both [[Absolute Indexed]] and [[Direct Page Indirect Indexed, Y]] admodes, EOR takes an extra cycle if adding the index crosses a page boundary.

=== See Also ===
* [[ORA]]
* [[AND]]
* [[EOR (SPC700)]]
* [[OR (SPC700)]]
* [[XOR (Super FX)]]

=== External Links ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/454 page 454] on EOR
# [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n151 page 141] on EOR
# 2.2.4.3 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n36 page 21] on EOR
# [[Carr]], [https://archive.org/details/6502UsersManual/page/n272 page 259] on EOR
# [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n112 page 3-63] on EOR
# snes9x implementation of EOR: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L533
# undisbeliever on EOR: https://undisbeliever.net/snesdev/65816-opcodes.html#eor-exclusive-or-accumulator-with-memory
# Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#EOR
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.1
# Carr, [https://archive.org/details/6502UsersManual/page/n273 page 260]

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]

DEC

2026-05-11T14:49:58Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Accumulator Addressing|Accumulator]]
|3A
|1 byte
|2 cycles
|+
|[[Absolute]]
|CE
|3 bytes
|6 cycles*
|+
|[[Direct Page Addressing | Direct Page]]
|C6
|2 bytes
|5 cycles*
|+
|[[Absolute Indexed by X]]
|DE
|3 bytes
|7 cycles*
|+
|[[Direct Page Indexed by X]]
|D6
|2 bytes
|6 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''DEC''' (Decrement) is a 65x instruction that decrements the value in the location specified by the operand by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low byte is located at the effective address and the high byte at the effective address plus one. An alternate mnemonic when the operand is the accumulator is "DEA."

DEC ignores the [[decimal mode flag]] and the [[carry flag]].

==== Syntax ====
<pre>
DEC
DEC A
DEA
DEC addr
DEC dp
DEC addr, X
DEC dp, X
</pre>

If you need to subtract two or more from the [[accumulator]], consider [[SBC]] instead.

==== Cycle Penalties ====
* Except in [[accumulator addressing]], DEC takes two extra cycles when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes (opcodes C6 and D6), DEC takes an extra cycle when the low byte of the [[direct page register]] is nonzero

Although the NMOS 6502 does have DEC, it does not work on the accumulator. The NES CPU is one such system that lacks that addressing mode for DEC. When porting code to the 65c816, utilizing DEC more often instead of SBC can make code smaller and faster.

=== See Also ===
* [[INC]]
* [[DEX]]
* [[DEY]]
* [[DEC (SPC700)]]
* [[DEC (Super FX)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/451 page 451] on DEC
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n148 page 138] on DEC
* 10.8 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n176 page 155] on DEC
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n270 page 257] on DEC
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n109 page 3-60] on DEC
* snes9x implementation of DEC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L482
* undisbeliever on DEC: https://undisbeliever.net/snesdev/65816-opcodes.html#dec-decrement
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#DEC
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.3

[[Category:ASM]]
[[Category:Group Two Instructions]]
[[Category:Read-Modify-Write Instructions]]
[[Category:Inherited from 6502]]

CMP

2026-05-11T14:45:33Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|C9
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|CD
|3 bytes
|4 cycles*
|+
|[[Absolute Long]]
|CF
|4 bytes
|5 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|C5
|2 bytes
|3 cycles*
|+
|[[Direct Page Indirect]]
|D2
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long]]
|C7
|2 bytes
|6 cycles*
|+
|[[Absolute Indexed by X]]
|DD
|3 bytes
|4 cycles*
|+
|[[Absolute Long Indexed by X]]
|DF
|4 bytes
|5 cycles*
|+
|[[Absolute Indexed by Y]]
|D9
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|D5
|2 bytes
|4 cycles*
|+
|[[Direct Page Indexed Indirect by X]]
|C1
|2 bytes
|6 cycles*
|+
|[[Direct Page Indirect Indexed by Y]]
|D1
|2 bytes
|5 cycles*
|+
|[[Direct Page Indirect Long Indexed by Y]]
|D7
|2 bytes
|6 cycles*
|+
|[[Stack Relative]]
|C3
|2 bytes
|4 cycles*
|+
|[[Stack Relative Indirect Indexed by Y]]
|D3
|2 bytes
|7 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|C
|}

'''CMP''' (Compare) is a 65x instruction that compares the value of the [[accumulator]] to something. Internally, this is done via a subtraction, but the difference is discarded. Thus, the purpose of CMP is to setup the flags. The accumulator serves as the minuend and the operand serves as the subtrahend. For example, CMP #6 does "a minus 6" internally. CMP only does unsigned comparisons. In [[immediate addressing]] only, CMP is a total of 3 bytes long when the accumulator is 16 bits wide. Unlike [[SBC]], the [[carry flag]] does not affect CMP.

The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

If the subtraction required a borrow, the carry flag is cleared (otherwise it is set).

The [[decimal mode flag]] has no effect on the behavior of CMP.

==== Syntax ====
<pre>
CMP #const
CMP addr
CMP long
CMP dp
CMP (dp)
CMP [dp]
CMP addr, X
CMP long, X
CMP addr, Y
CMP dp, X
CMP (dp, X)
CMP (dp), Y
CMP [dp], Y
CMP sr, S
CMP (sr, S), Y
</pre>

CPA is an alternative mnemonic. The 65c816 datasheet mentions an alternative mnemonic "CMA" which might be an alias for "CMP #0".

==== Cycle Penalties ====
* In all [[addressing modes]], CMP takes an extra cycle when the accumulator is 16 bits wide
* In [[direct page addressing]] modes (opcodes C5, D2, C7, D5, C1, D1, D7), CMP takes an extra cycle when the low byte of the [[direct page register]] is nonzero
* In both [[Absolute Indexed]] and [[Direct Page Indirect Indexed by Y]], CMP takes an extra cycle if adding the index crosses a page boundary

=== See Also ===
* [[CPX]]
* [[CPY]]
* [[CMP (Super FX)]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/445 page 445] on CMP
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n144 page 134] on CMP
* 4.2.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n60 page 45] on CMP
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n268 page 255] on CMP
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n105 page 3-56] on CMP
* snes9x implementation of CMP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L304
* undisbeliever on CMP: https://undisbeliever.net/snesdev/65816-opcodes.html#cmp-compare-accumulator-with-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#CMP
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.2

[[Category:ASM]]
[[Category:Group One Instructions]]
[[Category:Inherited from 6502]]
[[Category:Compare Instructions]]

BRK

2026-05-11T14:41:04Z

Xetheria: moved cycle penalty to bottom

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|00
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="9"|Flags Affected
|+
|
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]] / [[Break Flag|B]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[65c816 native mode]]
|.
|.
|.
|.
|0
|1
|.
|.
|+
|[[6502 emulation mode]]
|.
|.
|.
|1
|0
|1
|.
|.
|}

'''BRK''' (Break) is a 65x instruction that triggers a non-maskable software interrupt ([[Non-Maskable Interrupt|NMI]]). The byte following the opcode is called the [[signature byte]]. The state of the [[interrupt disable flag]] has no effect on the behavior of BRK although it will be set after BRK runs.

In [[native mode]] the [[program bank register]] is pushed to the [[stack]]. Then the [[program counter]] is incremented by two and then pushed to the stack. Then the [[status register]] (with the [[break flag]] set, if in emulation mode) is pushed to the stack. Then the interrupt disable flag is set. In native mode, the program bank register is then cleared.

Control is routed to the BRK handler, whose address is stored at the BRK vector:
* In native mode, this vector is at $00:FFE6.
* In emulation mode, this vector is at $FFFE.

==== Syntax ====
<pre>
BRK
BRK sig
</pre>

If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction. In this case the [[interrupt handler]] must decrement the [[return address]] on the [[stack]] so that the eventual [[RTI]] does not cause [[derailment]].

[[File:brk.png]]

BRK used to be considered a one-byte instruction in an early datasheet. On the NMOS 6502, BRK does not affect the decimal flag, but this likely only affects porting code from systems other than the NES because the NES does not have decimal mode anyway.

==== Cycle Skipped ====
* BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

=== See Also ===
* [[RTI]]
* [[BRK (SPC700)]]
* [[NMI]]
* [[IRQ]]
* [[COP]]
* [[WDM]]
* [[CLD]]
* [[SEI]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/436 page 436] on BRK
* Figure 13.3, Break Signature Byte Illustration, lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n136 page 126] on BRK
* 9.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n164 page 144] on BRK
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n265 page 252] on BRK
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n98 page 3-49] on BRK
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BRK
* Clark, Bruce. http://www.6502.org/tutorials/65c02opcodes.html#6
* https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

BIT

2026-05-11T14:37:49Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Immediate]]
|89
|2/3 bytes
|2 cycles*
|+
|[[Absolute]]
|2C
|3 bytes
|4 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|24
|2 bytes
|3 cycles*
|+
|[[Absolute Indexed by X]]
|3C
|3 bytes
|4 cycles*
|+
|[[Direct Page Indexed by X]]
|34
|2 bytes
|4 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|Addressing Mode
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[Immediate]]
|.
|.
|.
|.
|.
|.
|Z
|.
|+
|other
|N
|V
|.
|.
|.
|.
|Z
|.
|}

'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.

The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

Except in [[immediate addressing]], the most significant bit of the data located at the effective address (plus zero or one) is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].

==== Syntax ====
<pre>
BIT #const
BIT addr
BIT dp
BIT addr, X
BIT dp, X
</pre>

==== Cycle Penalties ====
* BIT takes an extra cycle when the accumulator is 16 bits wide, in all [[addressing modes]]
* In [[direct page addressing]] modes (opcodes 24 and 34), BIT takes an extra cycle when the low byte of the [[direct page register]] is nonzero
* In [[Absolute Indexed, X Addressing]] only, BIT takes an extra cycle when adding the index crosses a [[page]] boundary

=== See Also ===
* [[AND]]
* [[BPL]]
* [[BNE]]
* [[BCC]]
* [[BCS]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/431 page 431] on BIT
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n131 page 121] on BIT
* 4.2.2.1 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n62 page 47] on BIT
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n262 page 249] on BIT
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n94 page 3-45] on BIT
* snes9x implementation of BIT: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L265
* undisbeliever on BIT: https://undisbeliever.net/snesdev/65816-opcodes.html#bit-test-memory-bits-against-accumulator
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BIT
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.2

[[Category:ASM]]
[[Category:Group Three Instructions]]
[[Category:Inherited from 6502]]

ASL

2026-05-11T14:34:43Z

Xetheria: /* Cycle Penalties */ opcodes for dp admodes

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Accumulator Addressing|Accumulator]]
|0A
|1 byte
|2 cycles
|+
|[[Absolute]]
|0E
|3 bytes
|6 cycles*
|+
|[[Direct Page Addressing|Direct Page]]
|06
|2 bytes
|5 cycles*
|+
|[[Absolute Indexed by X]]
|1E
|3 bytes
|7 cycles*
|+
|[[Direct Page Indexed by X]]
|16
|2 bytes
|6 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|C
|}

'''ASL''' (Arithmetic Shift Left) is a 65x instruction that shifts every bit of a value left one bit (multiplication by two). The least significant bit is cleared. The most significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROL]]).

The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

==== Syntax ====
<pre>
ASL
ASL A
ASL addr
ASL dp
ASL addr, X
ASL dp, X
</pre>

==== Cycle Penalties ====
* Except in [[accumulator addressing]], ASL takes two extra cycles when the accumulator is 16 bits wide
* In [[direct page addressing]] modes (opcodes 06 and 16), ASL takes another extra cycle if the low byte of the [[direct page register]] is nonzero.

[[File:816_asl.png]]

=== See Also ===
* [[LSR]]
* [[ASL (SPC700)]]
* [[ROL]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/427 page 427] on ASL
* lbid [https://archive.org/details/0893037893ProgrammingThe65816/page/190 page 190], before & after diagram of ASL
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n127 page 117] on ASL
* 10.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n170 page 149] on ASL
* [https://archive.org/details/mos_microcomputers_programming_manual/page/n205 B-4], lbid.
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n260 page 247] on ASL
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n90 page 3-41] on ASL
* undisbeliever on ASL: https://undisbeliever.net/snesdev/65816-opcodes.html#asl-arithmetic-shift-left
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#ASL
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.3

[[Category:ASM]]
[[Category:Group Two Instructions]]
[[Category:Read-Modify-Write Instructions]]
[[Category:Inherited from 6502]]