SnesLab - User contributions [en]

Timing Control Unit

2026-04-09T23:41:56Z

Xetheria: clarify that this contains a counter

The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.

=== Reference ===
* section 2.2, page 6: https://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf

[[Category:SNES Hardware]]
[[Category:65c816]]

Reset Vector

2026-02-01T03:38:39Z

Xetheria: added table ref

The '''Reset Vector''' points to a subroutine that runs when the [[Control Deck]] first boots up or comes out of reset.

It is located at $00:FFFC,FD and is only active in [[emulation mode]].

=== See Also ===
* [[Interrupt Handler]]

=== Reference ===
* "Table 5-2 Emulation Mode Vector Locations (8-bit Mode)" on 65c816 datasheet, 2024 edition

[[Category:ASM]]

List of Anomie's Docs

2026-01-31T21:26:39Z

Xetheria: linkify bgmode

There are nine documents by anomie available on [[RHDN]]:

* [https://www.romhacking.net/documents/193 SNES Memory Mapping]
* [https://www.romhacking.net/documents/196 Register]
* [https://www.romhacking.net/documents/199 SNES Timing]
* [https://www.romhacking.net/documents/197 SPC700 with boot rom disassembly]
* [https://www.romhacking.net/documents/198 SPC700 Cycles]
* [https://www.romhacking.net/documents/191 S-DSP]
* [https://www.romhacking.net/documents/194 SNES OpenBus and Wrapping]
* [https://www.romhacking.net/documents/195 SNES Port]
* [https://www.romhacking.net/documents/192 C4 chip]

=== Errata ===
* In '''regs.txt''' under "BG Modes" we have "The SNES has 7 [[background modes]]," it should say 8.
* In the S-DSP doc, we have "Certain games do seem to depend on these exact formulas, trying to '''simplify''' will break some sound effects." But "approximate" would probably be clearer than "simplify," as in mathematics simplifying a formula only reduces the number of symbols used to express it, which may be easier to read but otherwise leaves it equivalent.

=== See Also ===
* [[List of Y0shi's Docs]]

[[Category:SNES Hardware]]
[[Category:Documents]]
[[Category:Lists]]

Priority Order Shifting

2026-01-31T01:26:01Z

Xetheria: /* References */ paragraph 20.3

'''Priority Order Shifting''' (or '''Priority Rotation''') refers to techniques that change which sprites appear on top or behind of other sprites.

While this can be done in software (by moving sprites around in [[OAM]]) the SNES contains a hardware feature for priority order shifting, bit 7 of OAMADDH (2103h):

* When clear, OBJ #0 has the highest priority.
* When set, the OBJ number specified by bits 1-7 of OAMADDL (2102h) has the highest priority.

=== References ===
* paragraph 20.3 on [https://archive.org/details/SNESDevManual/book1/page/n91 page 2-20-2 of Book I] of official Super Nintendo development manual
* https://www.problemkaputt.de/fullsnes.htm#snesmemoryoamaccessspriteattributes

[[Category:Video]]
[[Category:Official Jargon]]

Priority Order Shifting

2026-01-31T01:16:59Z

Xetheria: also called priority rotation

'''Priority Order Shifting''' (or '''Priority Rotation''') refers to techniques that change which sprites appear on top or behind of other sprites.

While this can be done in software (by moving sprites around in [[OAM]]) the SNES contains a hardware feature for priority order shifting, bit 7 of OAMADDH (2103h):

* When clear, OBJ #0 has the highest priority.
* When set, the OBJ number specified by bits 1-7 of OAMADDL (2102h) has the highest priority.

=== References ===
* [https://archive.org/details/SNESDevManual/book1/page/n91 page 2-20-2 of Book I] of official Super Nintendo development manual
* https://www.problemkaputt.de/fullsnes.htm#snesmemoryoamaccessspriteattributes

[[Category:Video]]
[[Category:Official Jargon]]

Priority Order Shifting

2026-01-31T01:10:55Z

Xetheria: linkify OAM

'''Priority Order Shifting''' refers to techniques that change which sprites appear on top or behind of other sprites.

While this can be done in software (by moving sprites around in [[OAM]]) the SNES contains a hardware feature for priority order shifting, bit 7 of OAMADDH (2103h):

* When clear, OBJ #0 has the highest priority.
* When set, the OBJ number specified by bits 1-7 of OAMADDL (2102h) has the highest priority.

=== References ===
* [https://archive.org/details/SNESDevManual/book1/page/n91 page 2-20-2 of Book I] of official Super Nintendo development manual
* https://www.problemkaputt.de/fullsnes.htm#snesmemoryoamaccessspriteattributes

[[Category:Video]]
[[Category:Official Jargon]]

Priority Order Shifting

2026-01-31T00:58:47Z

Xetheria: added ref, formatting

'''Priority Order Shifting''' refers to techniques that change which sprites appear on top or behind of other sprites.

While this can be done in software (by moving sprites around in OAM) the SNES contains a hardware feature for priority order shifting, bit 7 of OAMADDH (2103h):

* When clear, OBJ #0 has the highest priority.
* When set, the OBJ number specified by bits 1-7 of OAMADDL (2102h) has the highest priority.

=== References ===
* [https://archive.org/details/SNESDevManual/book1/page/n91 page 2-20-2 of Book I] of official Super Nintendo development manual
* https://www.problemkaputt.de/fullsnes.htm#snesmemoryoamaccessspriteattributes

[[Category:Video]]
[[Category:Official Jargon]]

Transfer Switches

2026-01-16T06:13:07Z

Xetheria: /* References */ hid archive URL

The '''Transfer Switches''' exist inside the [[65c816]]. They are connected to:

* Internal Address Bus
* Internal Special Bus
* Internal Data Bus

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/n604 page 578]
* Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram on page 8 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:SNES Hardware]]

Transfer Switches

2026-01-16T00:49:15Z

Xetheria: what they are connected to

The '''Transfer Switches''' exist inside the [[65c816]]. They are connected to:

* Internal Address Bus
* Internal Special Bus
* Internal Data Bus

=== References ===
* [[Eyes & Lichty]] page 578: https://archive.org/details/0893037893ProgrammingThe65816/page/n604
* Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram on page 8 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:SNES Hardware]]

Eyes & Lichty

2026-01-15T07:53:24Z

Xetheria: /* Errata */ spelling of "addressing"

"'''Eyes & Lichty'''" is scene slang for the excellent manual "Programming the 65816 Including the 6502, 65C02, and 65802" by David Eyes & Ron Lichty. It may be the best unofficial textbook on SNES programming, due in no small part to the fact that the [[Ricoh 5A22]] is based on the 65c816 and the [[SPC700]] is based on the 6502.

=== Addressing Mode ===
Eyes & Lichty divides the 65c816's various addressing modes into two groups: simple and complex. Simple addressing modes are explained first and require the processor to do little effective address calculation. They are:

==== Simple Addressing Modes ====
* [[Immediate]]
* [[Absolute]]
* [[Direct Page Addressing|Direct Page]]
* [[Accumulator Addressing|Accumulator]]
* [[Implied]]
* [[Stack Addressing|Stack]]
* [[Direct Page Indirect]]
* [[Absolute Long]]
* [[Direct Page Indirect Long]]
* [[Block Move Addressing|Block Move]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/108 page 108]

==== Complex Addressing Modes ====

* [[Absolute Indexed by X]]
* [[Absolute Indexed by Y]]
* [[Direct Page Indexed by X]]
* [[Direct Page Indexed by Y]]
* [[Direct Page Indirect Indexed by Y]]
* [[Direct Page Indexed Indirect by X]]
* [[Absolute Indexed Indirect]]
* Non-zero Direct Page
* [[Absolute Long Indexed by X]]
* [[Direct Page Indirect Long Indexed by Y]]
* [[Stack Relative]]
* [[Stack Relative Indirect Indexed by Y]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/197 page 197]

=== Errata ===
Applicable to the 2015 edition:
* Starting on page 389, several effective address diagrams have the bank byte labeled with too many zeros. Only two hex zero digits should fit in there.
* On page 498, opcode F5 has a "0" superscript on the # of cycles column.
* The [[stack]] diagram for [[RTI]] has the old [[status register]] value on the opposite side of the stack as the diagram for [[COP]]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/75 page 75] says the 65c816 has 25 different addressing modes, but the datasheet says there are 24
* [https://archive.org/details/0893037893ProgrammingThe65816/page/94 Page 94] says the 65c816 has three push instructions that do not alter registers: [[PEA]], [[PEI]], and [[PER]]. But the [[stack pointer]] itself is modified. Even not counting that, there are more than three, for example [[PHA]].
* [[PLB]] is not the only instruction that modifies the [[data bank register]]; [[MVP]] and [[MVN]] do too - see section 7.18 of the 65c816 datasheet
* In the section on [[accumulator addressing]], a sentence implies that all read-modify-write instructions are unary, but [[TRB]] and [[TSB]] are not.
* [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
* [https://archive.org/details/0893037893ProgrammingThe65816/page/510 Page 510] on [[TCD]] and page 512 on [[TDC]] mentions the [[direct page register]], but this is missing from the index
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no. Many readers would find a check mark less confusing.
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The 65c02 datasheet does mention [[WAI]] and [[STP]] are supported ([https://archive.org/details/0893037893ProgrammingThe65816/page/532 page 532] has them listed as unavailable)
* The [[addressing mode]] for [[WDM]] is missing, but the datasheet says it is [[Implied]]
* Assemblers are described as requiring the [[signature byte]] for [[COP]], but on the next page it says the signature byte is optional
* The page on [[PLA]] has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."
* Table 18.2 seems to imply that the [[M flag]] does not exist in [[emulation mode]] but the 65c816 datasheet says the M flag is always equal to one in emulation mode in section 2.8.

=== Quick Links ===

*[https://archive.org/details/0893037893ProgrammingThe65816/page/n7 Table of Contents]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n13 Preface]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n15 Acknowledgments]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n17 Foreword]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n19 Introduction]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n21 How to Use this Book]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n27 Part I Basics]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n29 Basic Assembly Language Programming Concepts]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n49 Part II Architecture]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n51 Architecture of the 6502]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n71 Architecture of the 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n75 Sixteen-Bit Architecture: The 65816 and the 65802]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n99 Part III Tutorial]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n101 SEP, REP, and Other Details]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n109 First Examples: Moving Data]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n133 The Simple Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n165 The Flow of Control]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n181 Built-In Arithmetic Functions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n205 Logic and Bit Manipulation Operations]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n223 The Complex Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n387 Design and Debugging]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n397 Reference]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n399 The Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n447 The Instruction Sets]
<div style="column-count:10">
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n449 ADC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n451 AND]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n453 ASL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n454 BCC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n455 BCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n456 BEQ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n457 BIT]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n458 BMI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n459 BNE]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n460 BPL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n461 BRA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n462 BRK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n463 BRL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n465 BVC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n466 BVS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n467 CLC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n468 CLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n469 CLI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n470 CLV]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n471 CMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n473 COP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n475 CPX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n476 CPY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n477 DEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n478 DEX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n479 DEY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n480 EOR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n482 INC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n483 INX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n484 INY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n485 JMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n486 JSL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n487 JSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n488 LDA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n489 LDX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n490 LDY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n491 LSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n492 MVN]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n493 MVP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n497 ORA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n499 PEA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n500 PEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n501 PER]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n502 PHA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n503 PHB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n504 PHD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n505 PHK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n506 PHP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n507 PHX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n508 PHY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n509 PLA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n510 PLB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n511 PLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n512 PLP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n513 PLX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n514 PLY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n515 REP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n516 ROL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n517 ROR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n518 RTI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n520 RTL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n522 RTS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n523 SBC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n525 SEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n526 SED]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n527 SEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n528 SEP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n529 STA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n530 STP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n531 STX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n532 STY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n533 STZ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n534 TAX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n535 TAY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n536 TCD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n537 TCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n538 TDC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n539 TRB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n540 TSB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n541 TSC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n542 TSX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n543 TXA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n544 TXS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n545 TXY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n546 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n547 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n548 WAI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n549 WDM]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n550 XBA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n551 XCE]
</div>
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n553 Instruction Lists]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n567 Appendices]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n569 65x Signal Description]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n577 65x Series Support Chips]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n587 The Rockwell 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n588 BBR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n589 BBS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n590 RMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n591 SMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n593 Instruction Groups]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n594 Group I Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n595 Group II Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n599 W65C816 Data Sheet]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n621 The ASCII Character Set]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n625 Index]

[[Category:ASM]]
[[Category:Books]]
[[Category:Scene Slang]]

Work RAM

2026-01-06T00:40:36Z

Xetheria: linkify refresh

[[File:wram schematic.png|thumb|The WRAM chip is straddling regions C1 and D1 in the [[jwdonal schematic]]]]

'''WRAM''' (Work RAM) serves as the SNES' main memory. It is 128K x 8 bits (131,072 bytes) in size, which is exactly two [[banks]]. It has part number 21326. [3] WRAM is located at $7E:0000.[1]

Even though WRAM has both [[Address Bus A]] and [[Address Bus B]] connected to it, the chip can only pay attention to one at a time, so WRAM-to-WRAM [[DMA]] isn't possible.

WRAM is left intact by a [[Reset]]. [2] But, Nintendo still recommendeds checking to make sure the contents are correct after a reset. [5] WRAM is DRAM and as such must be [[REFRESH and DRAMMODE|refreshed]].

[[Category:SNES Hardware]]
[[Category:Integrated Circuits]]
[[Category:ICs with unconnected pins]]
[[Category:Address Spaces]]

=== See Also ===
* [[ARAM]]
* [[VRAM]]
* [[OAM]]

=== References ===
# https://problemkaputt.de/fullsnes.htm#snesmemoryworkramaccess
# https://problemkaputt.de/fullsnes.htm#snescontrollersotherinputs
# [https://archive.org/details/SNESDevManual/book2/page/n404 page 1 of Book II], "Super NES Parts List" in the official Nintendo development manual
# paragraph 22.3 on [https://archive.org/details/SNESDevManual/book1/page/n97 page 2-22-1 of Book I], lbid
# caution #11: [https://archive.org/details/SNESDevManual/book1/page/n105 page 2-24-3 of Book I]

Set Overflow

2025-12-15T18:59:15Z

Xetheria: see also

The [[65c816]] has no SO pin.

=== See Also ===
* [[Overflow Flag]]

=== References ===
# [[Eyes & Lichty]] [https://archive.org/details/0893037893ProgrammingThe65816/page/546 page 546]
# http://www.6502.org/tutorials/vflag.html#4

[[Category:SNES Hardware]]

Set Overflow

2025-12-15T18:57:38Z

Xetheria: SO pin does not exist

The [[65c816]] has no SO pin.

=== References ===
# [[Eyes & Lichty]] page 546: [https://archive.org/details/0893037893ProgrammingThe65816/page/546 page 546]
# http://www.6502.org/tutorials/vflag.html#4

[[Category:SNES Hardware]]

Eyes & Lichty

2025-12-13T21:11:32Z

Xetheria: /* Errata */ linkify page 532

"'''Eyes & Lichty'''" is scene slang for the excellent manual "Programming the 65816 Including the 6502, 65C02, and 65802" by David Eyes & Ron Lichty. It may be the best unofficial textbook on SNES programming, due in no small part to the fact that the [[Ricoh 5A22]] is based on the 65c816 and the [[SPC700]] is based on the 6502.

=== Addressing Mode ===
Eyes & Lichty divides the 65c816's various addressing modes into two groups: simple and complex. Simple addressing modes are explained first and require the processor to do little effective address calculation. They are:

==== Simple Addressing Modes ====
* [[Immediate]]
* [[Absolute]]
* [[Direct Page Addressing|Direct Page]]
* [[Accumulator Addressing|Accumulator]]
* [[Implied]]
* [[Stack Addressing|Stack]]
* [[Direct Page Indirect]]
* [[Absolute Long]]
* [[Direct Page Indirect Long]]
* [[Block Move Addressing|Block Move]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/108 page 108]

==== Complex Addressing Modes ====

* [[Absolute Indexed by X]]
* [[Absolute Indexed by Y]]
* [[Direct Page Indexed by X]]
* [[Direct Page Indexed by Y]]
* [[Direct Page Indirect Indexed by Y]]
* [[Direct Page Indexed Indirect by X]]
* [[Absolute Indexed Indirect]]
* Non-zero Direct Page
* [[Absolute Long Indexed by X]]
* [[Direct Page Indirect Long Indexed by Y]]
* [[Stack Relative]]
* [[Stack Relative Indirect Indexed by Y]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/197 page 197]

=== Errata ===
Applicable to the 2015 edition:
* Starting on page 389, several effective address diagrams have the bank byte labeled with too many zeros. Only two hex zero digits should fit in there.
* On page 498, opcode F5 has a "0" superscript on the # of cycles column.
* The [[stack]] diagram for [[RTI]] has the old [[status register]] value on the opposite side of the stack as the diagram for [[COP]]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/75 page 75] says the 65c816 has 25 different addressesing modes, but the datasheet says there are 24
* [https://archive.org/details/0893037893ProgrammingThe65816/page/94 Page 94] says the 65c816 has three push instructions that do not alter registers: [[PEA]], [[PEI]], and [[PER]]. But the [[stack pointer]] itself is modified. Even not counting that, there are more than three, for example [[PHA]].
* [[PLB]] is not the only instruction that modifies the [[data bank register]]; [[MVP]] and [[MVN]] do too - see section 7.18 of the 65c816 datasheet
* In the section on [[accumulator addressing]], a sentence implies that all read-modify-write instructions are unary, but [[TRB]] and [[TSB]] are not.
* [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
* [https://archive.org/details/0893037893ProgrammingThe65816/page/510 Page 510] on [[TCD]] and page 512 on [[TDC]] mentions the [[direct page register]], but this is missing from the index
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no. Many readers would find a check mark less confusing.
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The 65c02 datasheet does mention [[WAI]] and [[STP]] are supported ([https://archive.org/details/0893037893ProgrammingThe65816/page/532 page 532] has them listed as unavailable)
* The [[addressing mode]] for [[WDM]] is missing, but the datasheet says it is [[Implied]]
* Assemblers are described as requiring the [[signature byte]] for [[COP]], but on the next page it says the signature byte is optional
* The page on [[PLA]] has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."
* Table 18.2 seems to imply that the [[M flag]] does not exist in [[emulation mode]] but the 65c816 datasheet says the M flag is always equal to one in emulation mode in section 2.8.

=== Quick Links ===

*[https://archive.org/details/0893037893ProgrammingThe65816/page/n7 Table of Contents]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n13 Preface]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n15 Acknowledgments]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n17 Foreword]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n19 Introduction]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n21 How to Use this Book]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n27 Part I Basics]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n29 Basic Assembly Language Programming Concepts]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n49 Part II Architecture]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n51 Architecture of the 6502]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n71 Architecture of the 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n75 Sixteen-Bit Architecture: The 65816 and the 65802]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n99 Part III Tutorial]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n101 SEP, REP, and Other Details]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n109 First Examples: Moving Data]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n133 The Simple Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n165 The Flow of Control]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n181 Built-In Arithmetic Functions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n205 Logic and Bit Manipulation Operations]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n223 The Complex Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n387 Design and Debugging]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n397 Reference]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n399 The Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n447 The Instruction Sets]
<div style="column-count:10">
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n449 ADC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n451 AND]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n453 ASL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n454 BCC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n455 BCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n456 BEQ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n457 BIT]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n458 BMI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n459 BNE]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n460 BPL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n461 BRA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n462 BRK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n463 BRL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n465 BVC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n466 BVS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n467 CLC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n468 CLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n469 CLI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n470 CLV]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n471 CMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n473 COP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n475 CPX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n476 CPY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n477 DEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n478 DEX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n479 DEY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n480 EOR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n482 INC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n483 INX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n484 INY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n485 JMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n486 JSL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n487 JSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n488 LDA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n489 LDX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n490 LDY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n491 LSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n492 MVN]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n493 MVP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n497 ORA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n499 PEA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n500 PEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n501 PER]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n502 PHA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n503 PHB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n504 PHD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n505 PHK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n506 PHP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n507 PHX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n508 PHY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n509 PLA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n510 PLB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n511 PLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n512 PLP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n513 PLX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n514 PLY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n515 REP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n516 ROL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n517 ROR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n518 RTI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n520 RTL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n522 RTS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n523 SBC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n525 SEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n526 SED]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n527 SEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n528 SEP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n529 STA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n530 STP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n531 STX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n532 STY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n533 STZ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n534 TAX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n535 TAY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n536 TCD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n537 TCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n538 TDC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n539 TRB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n540 TSB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n541 TSC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n542 TSX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n543 TXA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n544 TXS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n545 TXY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n546 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n547 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n548 WAI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n549 WDM]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n550 XBA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n551 XCE]
</div>
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n553 Instruction Lists]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n567 Appendices]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n569 65x Signal Description]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n577 65x Series Support Chips]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n587 The Rockwell 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n588 BBR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n589 BBS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n590 RMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n591 SMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n593 Instruction Groups]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n594 Group I Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n595 Group II Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n599 W65C816 Data Sheet]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n621 The ASCII Character Set]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n625 Index]

[[Category:ASM]]
[[Category:Books]]
[[Category:Scene Slang]]

Eyes & Lichty

2025-12-13T18:35:08Z

Xetheria: spelling of errata

"'''Eyes & Lichty'''" is scene slang for the excellent manual "Programming the 65816 Including the 6502, 65C02, and 65802" by David Eyes & Ron Lichty. It may be the best unofficial textbook on SNES programming, due in no small part to the fact that the [[Ricoh 5A22]] is based on the 65c816 and the [[SPC700]] is based on the 6502.

=== Addressing Mode ===
Eyes & Lichty divides the 65c816's various addressing modes into two groups: simple and complex. Simple addressing modes are explained first and require the processor to do little effective address calculation. They are:

==== Simple Addressing Modes ====
* [[Immediate]]
* [[Absolute]]
* [[Direct Page Addressing|Direct Page]]
* [[Accumulator Addressing|Accumulator]]
* [[Implied]]
* [[Stack Addressing|Stack]]
* [[Direct Page Indirect]]
* [[Absolute Long]]
* [[Direct Page Indirect Long]]
* [[Block Move Addressing|Block Move]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/108 page 108]

==== Complex Addressing Modes ====

* [[Absolute Indexed by X]]
* [[Absolute Indexed by Y]]
* [[Direct Page Indexed by X]]
* [[Direct Page Indexed by Y]]
* [[Direct Page Indirect Indexed by Y]]
* [[Direct Page Indexed Indirect by X]]
* [[Absolute Indexed Indirect]]
* Non-zero Direct Page
* [[Absolute Long Indexed by X]]
* [[Direct Page Indirect Long Indexed by Y]]
* [[Stack Relative]]
* [[Stack Relative Indirect Indexed by Y]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/197 page 197]

=== Errata ===
Applicable to the 2015 edition:
* Starting on page 389, several effective address diagrams have the bank byte labeled with too many zeros. Only two hex zero digits should fit in there.
* On page 498, opcode F5 has a "0" superscript on the # of cycles column.
* The [[stack]] diagram for [[RTI]] has the old [[status register]] value on the opposite side of the stack as the diagram for [[COP]]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/75 page 75] says the 65c816 has 25 different addressesing modes, but the datasheet says there are 24
* [https://archive.org/details/0893037893ProgrammingThe65816/page/94 Page 94] says the 65c816 has three push instructions that do not alter registers: [[PEA]], [[PEI]], and [[PER]]. But the [[stack pointer]] itself is modified. Even not counting that, there are more than three, for example [[PHA]].
* [[PLB]] is not the only instruction that modifies the [[data bank register]]; [[MVP]] and [[MVN]] do too - see section 7.18 of the 65c816 datasheet
* In the section on [[accumulator addressing]], a sentence implies that all read-modify-write instructions are unary, but [[TRB]] and [[TSB]] are not.
* [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
* [https://archive.org/details/0893037893ProgrammingThe65816/page/510 Page 510] on [[TCD]] and page 512 on [[TDC]] mentions the [[direct page register]], but this is missing from the index
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no. Many readers would find a check mark less confusing.
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The 65c02 datasheet does mention [[WAI]] and [[STP]] are supported (page 532 has them listed as unavailable)
* The [[addressing mode]] for [[WDM]] is missing, but the datasheet says it is [[Implied]]
* Assemblers are described as requiring the [[signature byte]] for [[COP]], but on the next page it says the signature byte is optional
* The page on [[PLA]] has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."
* Table 18.2 seems to imply that the [[M flag]] does not exist in [[emulation mode]] but the 65c816 datasheet says the M flag is always equal to one in emulation mode in section 2.8.

=== Quick Links ===

*[https://archive.org/details/0893037893ProgrammingThe65816/page/n7 Table of Contents]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n13 Preface]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n15 Acknowledgments]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n17 Foreword]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n19 Introduction]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n21 How to Use this Book]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n27 Part I Basics]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n29 Basic Assembly Language Programming Concepts]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n49 Part II Architecture]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n51 Architecture of the 6502]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n71 Architecture of the 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n75 Sixteen-Bit Architecture: The 65816 and the 65802]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n99 Part III Tutorial]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n101 SEP, REP, and Other Details]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n109 First Examples: Moving Data]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n133 The Simple Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n165 The Flow of Control]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n181 Built-In Arithmetic Functions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n205 Logic and Bit Manipulation Operations]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n223 The Complex Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n387 Design and Debugging]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n397 Reference]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n399 The Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n447 The Instruction Sets]
<div style="column-count:10">
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n449 ADC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n451 AND]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n453 ASL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n454 BCC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n455 BCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n456 BEQ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n457 BIT]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n458 BMI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n459 BNE]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n460 BPL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n461 BRA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n462 BRK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n463 BRL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n465 BVC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n466 BVS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n467 CLC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n468 CLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n469 CLI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n470 CLV]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n471 CMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n473 COP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n475 CPX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n476 CPY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n477 DEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n478 DEX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n479 DEY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n480 EOR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n482 INC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n483 INX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n484 INY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n485 JMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n486 JSL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n487 JSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n488 LDA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n489 LDX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n490 LDY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n491 LSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n492 MVN]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n493 MVP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n497 ORA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n499 PEA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n500 PEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n501 PER]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n502 PHA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n503 PHB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n504 PHD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n505 PHK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n506 PHP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n507 PHX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n508 PHY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n509 PLA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n510 PLB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n511 PLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n512 PLP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n513 PLX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n514 PLY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n515 REP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n516 ROL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n517 ROR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n518 RTI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n520 RTL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n522 RTS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n523 SBC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n525 SEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n526 SED]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n527 SEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n528 SEP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n529 STA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n530 STP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n531 STX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n532 STY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n533 STZ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n534 TAX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n535 TAY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n536 TCD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n537 TCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n538 TDC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n539 TRB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n540 TSB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n541 TSC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n542 TSX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n543 TXA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n544 TXS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n545 TXY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n546 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n547 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n548 WAI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n549 WDM]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n550 XBA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n551 XCE]
</div>
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n553 Instruction Lists]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n567 Appendices]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n569 65x Signal Description]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n577 65x Series Support Chips]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n587 The Rockwell 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n588 BBR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n589 BBS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n590 RMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n591 SMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n593 Instruction Groups]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n594 Group I Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n595 Group II Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n599 W65C816 Data Sheet]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n621 The ASCII Character Set]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n625 Index]

[[Category:ASM]]
[[Category:Books]]
[[Category:Scene Slang]]

Emulation Mode Flag

2025-12-13T10:02:56Z

Xetheria: added very rare address space straddling quirk

The '''Emulation Mode Flag''' (E) controls whether the [[65c816]] is behaving like a 6502:
* When clear, the '816 is in '''65c816 native mode.'''
* When set, the '816 is in '''6502 emulation mode.'''

This flag cannot be modified directly and is normally hidden from the programmer. To modify it, use the [[XCE]] instruction to swap its value with the [[carry flag]]'s value. This treats the [[status register]] bits as a game of musical chairs.

The designers likely omitted CLE and SEE opcodes to set or clear it directly because dedicating two opcodes to such a rare operation is overkill.

The flag is set when a [[RESET]] interrupt is fired. In other words, the CPU always starts in emulation mode at boot and after a reset.

Emulation mode is not perfect. Some important behavior differences from the 6502 are:
* The 65c816 does not attempt to emulate the illegal 6502 opcodes because its [[65c816 Opcode Matrix|opcode matrix]] is already full. All 256 opcodes work in both native and emulation mode, but many are less useful in emulation mode.[3]
* The [[direct page]] is fully relocatable in both native and emulation mode even though it doesn't exist on the 6502, so pointing it to the zero page right before running 6502 code is advised to ensure maximum compatibility
* Direct page indexed addressing will always wrap around and remain within the direct page in emulation mode, instead of possibly crossing over into the next page. ([[E&L]], [https://archive.org/details/0893037893ProgrammingThe65816/page/374 page 374])
* The [[program bank register]] and [[data bank register]] still exist in emulation mode even though they don't exist on a 6502, so memory accesses may not always access bank zero.
* the hidden [[B accumulator]] still exists in emulation mode even though it does not on a 6502
* (''very rare)'' 6502 code trying to load the word straddling the end of the 16-bit address space will instead cross over into the next bank in emulation mode.[5]

For writing new SNES code it is recommended to almost always stay in native mode even if dealing with 8 bit data. Some reasons are:
* Page boundary crossings incur a one cycle penalty in emulation mode. Emulation mode emulates the NMOS 6502 cycle counts.
* Large amounts of 8-bit data can sometimes be processed in 16-bit chunks, and doing so can take fewer loads/stores/transfers than treating them as 8-bit.
* The [[break flag]] need not be examined in native mode because there are more interrupt vectors. (In fact, it does not even exist).

On the other hand, [[COP]], [[BRK]], and [[RTI]] take one extra cycle in native mode because of the [[bank]] number. For running 6502 code with minimal issues it is still recommended to use emulation mode. For example, one quirk of 8-bit native mode is that [[TXS]] points the [[stack]] to the [[zeropage]].

Emulation code need not be in [[bank]] 0.

In emulation mode, the [[stack pointer]]'s high byte is always one. The M and X flags are always set in emulation mode.[4]

=== See Also ===
* [[SA-1]]

=== References ===
# Figure 17.3, [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#APPENDIX
# section 7.8 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.8, lbid.
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.12

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

Category:Transfer Instructions

2025-12-12T19:35:32Z

Xetheria: note about counterparts, TRB and TSB

These are [[65c816]] instructions whose mnemonic begins with "T" for "Transfer." By exchanging the second and third letter of the mnemonic you can always find the counterpart to transfer in the opposite direction.

The only two transfer instructions that do not alter any flags are [[TCS]] and [[TXS]].

[[TRB]] and [[TSB]] are the only non-transfer 65c816 instructions that begin with "T".

[[Category:ASM]]
[[Category:One-byte Instructions]]
[[Category:Two-cycle Instructions]]

Direct Page Indirect Addressing

2025-12-12T16:01:09Z

Xetheria: emulation mode quirk

'''Direct Page Indirect Addressing''' is supported by eight instructions:

* [[ADC]] (opcode 72)
* [[AND]] (opcode 32)
* [[CMP]] (opcode D2)
* [[EOR]] (opcode 52)
* [[LDA]] (opcode B2)
* [[ORA]] (opcode 12)
* [[SBC]] (opcode F2)
* [[STA]] (opcode 92)

==== Syntax ====
<pre>
LDA (dp)
</pre>

In the above example, the 16-bit address stored at location dp of the direct page is fetched, and then the accumulator is loaded with the byte that lives at that address.

In [[emulation mode]], the 16-bit pointer can't straddle a page boundary.[4]

=== See Also ===
* [[Direct Page Indirect Long Addressing]]
* [[Direct Page Addressing]]

=== References ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/393 page 393]
# [https://archive.org/details/0893037893ProgrammingThe65816/page/128 page 128], lbid
# section 3.5.16 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.9

[[Category:Addressing Modes]]
[[Category:Simple Admodes]]
[[Category:ASM]]
[[Category:65c816 additions]]

Talk:Emulation Mode Flag

2025-12-12T14:25:04Z

Xetheria: might want to remove bullet point

Can't seem to get Bruce Clark link working here.

Might want to remove/move that bullet point on direct page wrapping - that whole set of bullet points are about differences between running code on a real 6502 and running it in emulation mode on a 65816, not how a 65816 feature normally behaves

TAY

2025-12-12T11:00:01Z

Xetheria: does not care how wide accumulator is

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Implied]] (type 1)
|A8
|1 byte
|2 cycles
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''TAY''' is a 65x instruction that transfers the value of the [[accumulator]] to the [[Y index register]]. The size of the Y index register determines how many bytes are transferred. TAY does not care how wide the accumulator is. TAY always takes two cycles, regardless of whether one or two bytes are transferred.

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="3"|Instruction Behavior
|+
|
|'''8-bit accumulator (m=1)'''
|'''16-bit accumulator (m=0)'''
|+
|'''8-bit index registers (x=1)'''
|8 bits are transferred
|8 bits are transferred (low byte of accumulator)
|+
|'''16-bit index registers (x=0)'''
|16 bits are transferred (including hidden upper byte)
|16 bits are transferred (full C accumulator)
|}

==== Syntax ====
<pre>
TAY
</pre>

=== See Also ===
* [[TAX]]
* [[TYA]]
* [[TCD]]
* [[TCS]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/509 page 509] on TAY
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n200 page 190] on TAY
* 7.13 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n119 page 101] on TAY
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n149 page 3-100] on TAY
* snes9x implementation of TAY: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2289

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Transfer Instructions]]
[[Category:Implied Instructions]]
[[Category:Two-cycle Instructions]]

TAX

2025-12-12T10:56:17Z

Xetheria: does not care how wide accumulator is

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Implied]] (type 1)
|AA
|1 byte
|2 cycles
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''TAX''' is a 65x instruction that transfers the value of the [[accumulator]] to the [[X index register]]. The size of the X index register determines how many bytes are transferred. TAX does not care how wide the accumulator is. TAX always takes two cycles, regardless of whether one or two bytes are transferred.

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="3"|Instruction Behavior
|+
|
|'''8-bit accumulator (m=1)'''
|'''16-bit accumulator (m=0)'''
|+
|'''8-bit index registers (x=1)'''
|8 bits are transferred
|8 bits are transferred (low byte of accumulator)
|+
|'''16-bit index registers (x=0)'''
|16 bits are transferred (including hidden upper byte)
|16 bits are transferred (full C accumulator)
|}

==== Syntax ====
<pre>
TAX
</pre>

=== See Also ===
* [[TAY]]
* [[TXA]]
* [[TCD]]
* [[TCS]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/508 page 508] on TAX
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n199 page 189] on TAX
* 7.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n118 page 100] on TAX
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n288 page 275] on TAX
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n148 page 3-99] on TAX
* snes9x implementation of TAX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2258

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Transfer Instructions]]
[[Category:Implied Instructions]]
[[Category:Two-cycle Instructions]]

SA-1

2025-12-01T07:25:15Z

Xetheria: /* Features */ base is slowrom

'''Nintendo SA-1''' (Super Accelerator) is an [[enhancement chip]] made by [http://en.wikipedia.org/wiki/Nintendo Nintendo], used in 33 SNES games. The RF5A123 chip is based on the [[65c816]] processor, the same one used by the main SNES CPU, the [[RF5A22]]. With identical architecture to the SNES one, the chip is ideal for games and ROM hacks that can reuse code from the main CPU, thus not having to learn an additional assembling language or architecture.

When you are on the SA-1 context, the SA-1 CPU is often referred as "C-CPU" ("C" stands for co-processor) while the SNES CPU is often referred as "S-CPU" ("S" stands for SNES). There is no master or slave, because both processors can interrupt each other though [[IRQ]]s, keeping in mind that initially SA-1 boots up in the sleeping state and must be initialized by the SNES CPU.

{{TOClimit|4}}

== Features ==

The embedded co-processor has a '''10.74 MHz''' base clock speed, which is four times faster compared to the 2.68 MHz base clock speed from the S-CPU (a.k.a. [[SlowROM]]). In addition to that, it includes additional hardware circuits for data I/O, bitmap manipulation modes, arithmetic registers and high-speed internal memory.

* 16-bit 65c816 processor clocked at 10.74 MHz.
* 2 kB internal work memory (I-RAM), clocked at 10.74 MHz.
* Multi-processor processing, with parallel operating mode and automatic memory sharing control.
* Large capacity memory, with a total capability of 8 MB ROM and 256 kB BW-RAM, both clocked at 5.37 MHz, with ROM having an effective 10.74 MHz speed because of the 16-bit data bus.
* High speed arithmetic multiplication, division and cumulative sum (multiply with add) hardware.
* Bitmap and Character Conversion functions for fast graphics manipulation.
* Custom DMA circuit for fast transfers between ROM, I-RAM and BW-RAM.
* Variable-Length Bit data processing for enhanced algorithms such as graphics and data compression.
* Super MMC memory mapping capabilities for BW-RAM and bank switching for multiple ROM image access and mirroring.

== ROM Hacking ==

[[SA-1 Root]] and [[SA-1 Pack]] are known patches used for enabling SA-1 on SNES games that didn't include the chip previously and had problems with slowdown, such as ''[[Super Mario World]]'', ''[[Gradius III]]'' and ''[[Contra III]]''.

= Technical Information =
There is not much technical information available on how the SA-1 chip works. Most of the findings are recent and are based on both official documents from Nintendo and experiments on real SA-1 carts. This section is getting continuously updated with new information and findings though the time. The information available here is expected to be accurate. Information about undefined behavior or design details is considered scarce right now.

== Hardware Registers ==
The SA-1 internal registers are assigned on range $2200-$23FF, on banks $00-$3F and $80-$BF. $2200 though $22FF are write-only registers while $2300 though $23FF are read-only registers.

* Attempting to read a write-only register yields [[open bus]].
* Attempting to write a SA-1 write register on SNES side or vice-versa yields nothing, with the exception of hybrid write registers.
* Attempting to read a SA-1 read register on SNES side or vice-versa yields open bus.

=== Register Summary ===

==== Write Registers ====

{| class="wikitable"
|-
! Address !! Length !! Code !! Access !! Description
|-
| $2200 || 1 byte || CCNT || SNES || SA-1 CPU CONTROL
|-
| $2201 || 1 byte || SIE || SNES || SUPER NES CPU INT ENABLE
|-
| $2202 || 1 byte || SIC || SNES || SUPER NES CPU INT CLEAR
|-
| $2203 || 2 bytes || CRV || SNES || SA-1 CPU RESET VECTOR
|-
| $2205 || 2 bytes || CNV || SNES || SA-1 CPU NMI VECTOR
|-
| $2207 || 2 bytes || CIV || SNES || SA-1 CPU IRQ VECTOR
|-
| $2209 || 1 byte || SCNT || SA-1 || SUPER NES CPU CONTROL
|-
| $220A || 1 byte || CIE || SA-1 || SA-1 CPU INT ENABLE
|-
| $220B || 1 byte || CIC || SA-1 || SA-1 CPU INT CLEAR
|-
| $220C || 2 bytes || SNV || SA-1 || SUPER NES CPU NMI VECTOR
|-
| $220E || 2 bytes || SIV || SA-1 || SUPER NES CPU IRQ VECTOR
|-
| $2210 || 1 byte || TMC || SA-1 || H/V TIMER CONTROL
|-
| $2211 || 1 byte || CTR || SA-1 || SA-1 CPU TIMER RESTART
|-
| $2212 || 2 bytes || HCNT || SA-1 || SET H-COUNT
|-
| $2214 || 2 bytes || VCNT || SA-1 || SET V-COUNT
|-
| $2220 || 1 byte || CXB || SNES || SET SUPER MMC BANK C
|-
| $2221 || 1 byte || DXB || SNES || SET SUPER MMC BANK D
|-
| $2222 || 1 byte || EXB || SNES || SET SUPER MMC BANK E
|-
| $2223 || 1 byte || FXB || SNES || SET SUPER MMC BANK F
|-
| $2224 || 1 byte || BMAPS || SNES || SUPER NES CPU BW-RAM ADDRESS MAPPING
|-
| $2225 || 1 byte || BMAP || SA-1 || SA-1 CPU BW-RAM ADDRESS MAPPING
|-
| $2226 || 1 byte || SBWE || SNES || SUPER NES CPU BW-RAM WRITE ENABLE
|-
| $2227 || 1 byte || CBWE || SA-1 || SA-1 CPU BW-RAM WRITE ENABLE
|-
| $2228 || 1 byte || BPWA || SNES || BW-RAM WRITE-PROTECTED AREA
|-
| $2229 || 1 byte || SIWP || SNES || SA-1 I-RAM WRITE PROTECTION
|-
| $222A || 1 byte || CIWP || SA-1 || SA-1 I-RAM WRITE PROTECTION
|-
| $2230 || 1 byte || DCNT || SA-1 || DMA CONTROL
|-
| $2231 || 1 byte || CDMA || Both || CHARACTER CONVERSION OMA PARAMETERS
|-
| $2232 || 3 bytes || SDA || Both || DMA SOURCE DEVICE START ADDRESS
|-
| $2235 || 3 bytes || DDA || Both || DMA DESTINATION START ADDRESS
|-
| $2238 || 2 bytes || DTC || SA-1 || DMA TERMINAL COUNTER
|-
| $223F || 1 byte || BBF || SA-1 || BW-RAM BIT MAP FORMAT
|-
| $2240 || 16 bytes || BRF || SA-1 || BIT MAP REGISTER FILE
|-
| $2250 || 1 byte || MCNT || SA-1 || ARITHMETIC CONTROL
|-
| $2251 || 2 bytes || MA || SA-1 || ARITHMETIC PARAMETERS: MULTIPLICAND/DIVIDEND
|-
| $2253 || 2 bytes || MB || SA-1 || ARITHMETIC PARAMETERS: MULTIPLIER/DIVISOR
|-
| $2258 || 1 byte || VBD || SA-1 || VARIABLE-LENGTH BIT PROCESSING
|-
| $2259 || 3 bytes || VDA || SA-1 || VARIABLE-LENGTH BIT GAME PAK ROM START ADDRESS
|}

==== Read Registers ====

{| class="wikitable"
|-
! Address !! Length !! Code !! Access !! Description
|-
| $2300 || 1 bytes || SFR || SNES || SUPER NES CPU FLAG READ
|-
| $2301 || 1 bytes || CFR || SA-1 || SA-1 CPU FLAG READ
|-
| $2302 || 2 bytes || HCR || SA-1 || H-COUNT READ
|-
| $2304 || 2 bytes || VCR || SA-1 || V-COUNT READ
|-
| $2306 || 5 bytes || MR || SA-1 || ARITHMETIC RESULT [PRODUCT/QUOTIENT/ACCUMULATIVE SUM]
|-
| $230B || 1 bytes || OF || SA-1 || ARITHMETIC OVERFLOW FLAG
|-
| $230C || 2 bytes || VDP || SA-1 || VARIABLE-LENGTH DATA READ PORT
|-
| $230E || 1 byte || VC || SNES || VERSION CODE REGISTER (OPEN BUS)
|}

=== Register Details ===

==== $2200 - SA-1 CPU CONTROL ====

==== $2201 - SUPER NES CPU INT ENABLE ====

==== $2202 - SUPER NES CPU INT CLEAR ====

==== $2203 - SA-1 CPU RESET VECTOR ====

==== $2205 - SA-1 CPU NMI VECTOR ====

==== $2207 - SA-1 CPU IRQ VECTOR ====

==== $2209 - SUPER NES CPU CONTROL ====

==== $220A - SA-1 CPU INT ENABLE ====

==== $220B - SA-1 CPU INT CLEAR ====

==== $220C - SUPER NES CPU NMI VECTOR ====

==== $220E - SUPER NES CPU IRQ VECTOR ====

==== $2210 - H/V TIMER CONTROL ====

==== $2211 - SA-1 CPU TIMER RESTART ====

==== $2212 - SET H-COUNT ====

==== $2214 - SET V-COUNT ====

==== $2220-$2223 - SET SUPER MMC BANK C/D/E/F ====
{{32bit-reg|2220|2221|2222|2223
|CBM|0|0|0|0|CB2|CB1|CB0
|DBM|0|0|0|0|CB2|CB1|CB0
|EBM|0|0|0|0|CB2|CB1|CB0
|FBM|0|0|0|0|CB2|CB1|CB0}}

CB2~CB0: Which megabyte of the ROM to map to $C0-$CF / $D0-$DF / $E0-$EF / $F0-$FF.

CBM/DBM/EBM/FBM: If set, apply image projection to LoROM banks as well.
{|style="width:auto"
|-
! Flag !! Bank Range
|-
| CBM || Apply to banks $00-$1F
|-
| DBM || Apply to banks $20-$3F
|-
| EBM || Apply to banks $80-$9F
|-
| FBM || Apply to banks $A0-$BF
|}

Registers are responsible for setting up the ROM bank mapping.
By default, the values { $00, $01, $02, $03 } are loaded on power up.

Bits CBM/DBM/EBM/FBM determine if the mapping should apply to the LoROM banks as well, otherwise they will have the constant value of { $00, $01, $02, $03 } regardless of the ROM size. Given that, it's possible the entire 8 MB layout at once by storing values { $04, $05, $06, $07 } to the registers. Snes9x 1.53 and older always treated these flags as set, making the mapping always apply to the LoROM banks.

{|style="width:auto"
|+Common values
|-
! Register !! $2220 !! $2221 !! $2222 !! $2223 !! Comment
|-
| Value || $00 || $01 || $02 || $03 || Default values
|-
| Value || $04 || $05 || $06 || $07 || Maps the first 4 MB to banks $00-$3F and $80-$BF, with LoROM-like layout. The last 4 MB is mapped to $C0-$FF, with HiROM-like layout.
|-
| Value || $80 || $81 || $80 || $81 || Simulates the standard LoROM map with FastROM compatibility by mapping the first 2 MB to $00-$3F and $80-$BF.
|}

The Super MMC register affects all memory maps, including SNES, SA-1, SA-1 DMA and SA-1 Variable Length Bit maps.
bsnes 0.7x does not apply the custom memory mapping to Variable Length Bit circuit.

Hardware verification has shown that the unused bits has no effects to the chip pinout and therefore the maximum ROM size for the SA-1 without using a custom ROM controller outside the chip is 8 MB (megabytes).

==== $2224 - SUPER NES CPU BW-RAM ADDRESS MAPPING ====

==== $2225 - SA-1 CPU BW-RAM ADDRESS MAPPING ====

==== $2226 - SUPER NES CPU BW-RAM WRITE ENABLE ====

==== $2227 - SA-1 CPU BW-RAM WRITE ENABLE ====

==== $2228 - BW-RAM WRITE-PROTECTED AREA ====

==== $2229 - SA-1 I-RAM WRITE PROTECTION ====

==== $222A - SA-1 I-RAM WRITE PROTECTION ====

==== $2230 - DMA CONTROL ====

==== $2231 - CHARACTER CONVERSION OMA PARAMETERS ====

==== $2232 - DMA SOURCE DEVICE START ADDRESS ====

==== $2235 - DMA DESTINATION START ADDRESS ====

==== $2238 - DMA TERMINAL COUNTER ====

==== $223F - BW-RAM BIT MAP FORMAT ====
{{8bit-reg|223F|SEL42|-|-|-|-|-|-|-}}
{| style="width:auto"
|-
! Bits !! Meaning
|-
| SEL42 || 0 to make banks $60-$6F split in 4 bits chunks (4BPP) or 1 to split in 2 bits chunks (2BPP)
|}

==== $2240 - BIT MAP REGISTER FILE ====

==== $2250 - ARITHMETIC CONTROL ====

==== $2251 - ARITHMETIC PARAMETERS: MULTIPLICAND/DIVIDEND ====

==== $2253 - ARITHMETIC PARAMETERS: MULTIPLIER/DIVISOR ====

==== $2258 - VARIABLE-LENGTH BIT PROCESSING ====

==== $2259 - VARIABLE-LENGTH BIT GAME PAK ROM START ADDRESS ====

==== $2300 - SUPER NES CPU FLAG READ ====

==== $2301 - SA-1 CPU FLAG READ ====

==== $2302 - H-COUNT READ ====

==== $2304 - V-COUNT READ ====

==== $2306 - ARITHMETIC RESULT [PRODUCT/QUOTIENT/ACCUMULATIVE SUM] ====

==== $230B - ARITHMETIC OVERFLOW FLAG ====

==== $230C - VARIABLE-LENGTH DATA READ PORT ====

==== $230E - VERSION CODE REGISTER (OPEN BUS) ====
{{8bit-reg|230E|VC7|VC6|VC5|VC4|VC3|VC2|VC1|VC0}}
{| style="width:auto"
|-
! Bits !! Meaning
|-
| VC0 ~ VC7 || SA-1 Device Version
|}
According the SNES Development Book II, this register was supposed to hold the SA-1 chip version code, however tests made on some real carts has shown that this register in particular is actually [[open bus]].
-----

== Memory and Bus ==

=== Memory Map ===

==== SNES Side ====

==== SA-1 Side ====

==== Open Bus Behavior ====

=== ROM ===

=== I-RAM ===

==== Write Protection ====

=== BW-RAM ===

==== Write Protection ====

=== Virtual Bitmap Memory ===

=== Super MMC ===

=== Bus Conflicts ===

== Direct Memory Access ==

=== Character Conversion DMA ===

=== Parallel DMA ===

=== Interactions with SNES DMA ===

=== Undefined Behavior ===

== Variable Length Bit ==

=== Fixed Mode ===

=== Automatic Mode ===

=== Mixed Mode ===

== Arithmetic Operations ==

=== Multiplication ===

=== Division ===

=== Cumulative Sum ===

== Parallelism and I/O ==

=== IRQ ===

=== NMI ===

=== FastROM Interactions ===

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Integrated Circuits]]
[[Category:Enhancement Chips]]
[[Category:SA-1]]

SYSCK

2025-11-30T06:26:46Z

Xetheria: System Clock

'''SYSCK''' (System Clock) is a signal that is produced by the [[S-CPU]], coming out of pin 72. It goes into:

* pin 6 of [[WRAM]].
* pin pad 57 of the [[Cartridge Slot]] (both [[List of 46-pin Games|46-pin]] and [[List of 62-pin Games|62-pin]] cartridges have this pin)

According to the [[jwdonal schematic]], it is most likely the current memory access cycle clock.

=== See Also ===
* [[Master Clock]]
* [[FastROM]]
* [[SlowROM]]

[[Category:SNES Hardware]]
[[Category:Traces]]

SYSCLK

2025-11-30T06:24:08Z

Xetheria: created page

#redirect [[SYSCK]]

Eyes & Lichty

2025-11-28T08:04:40Z

Xetheria: /* Eratta */ M flag does always exist

"'''Eyes & Lichty'''" is scene slang for the excellent manual "Programming the 65816 Including the 6502, 65C02, and 65802" by David Eyes & Ron Lichty. It may be the best unofficial textbook on SNES programming, due in no small part to the fact that the [[Ricoh 5A22]] is based on the 65c816 and the [[SPC700]] is based on the 6502.

=== Addressing Mode ===
Eyes & Lichty divides the 65c816's various addressing modes into two groups: simple and complex. Simple addressing modes are explained first and require the processor to do little effective address calculation. They are:

==== Simple Addressing Modes ====
* [[Immediate]]
* [[Absolute]]
* [[Direct Page Addressing|Direct Page]]
* [[Accumulator Addressing|Accumulator]]
* [[Implied]]
* [[Stack Addressing|Stack]]
* [[Direct Page Indirect]]
* [[Absolute Long]]
* [[Direct Page Indirect Long]]
* [[Block Move Addressing|Block Move]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/108 page 108]

==== Complex Addressing Modes ====

* [[Absolute Indexed by X]]
* [[Absolute Indexed by Y]]
* [[Direct Page Indexed by X]]
* [[Direct Page Indexed by Y]]
* [[Direct Page Indirect Indexed by Y]]
* [[Direct Page Indexed Indirect by X]]
* [[Absolute Indexed Indirect]]
* Non-zero Direct Page
* [[Absolute Long Indexed by X]]
* [[Direct Page Indirect Long Indexed by Y]]
* [[Stack Relative]]
* [[Stack Relative Indirect Indexed by Y]]

see [https://archive.org/details/0893037893ProgrammingThe65816/page/197 page 197]

=== Eratta ===
Applicable to the 2015 edition:
* Starting on page 389, several effective address diagrams have the bank byte labeled with too many zeros. Only two hex zero digits should fit in there.
* On page 498, opcode F5 has a "0" superscript on the # of cycles column.
* The [[stack]] diagram for [[RTI]] has the old [[status register]] value on the opposite side of the stack as the diagram for [[COP]]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/75 page 75] says the 65c816 has 25 different addressesing modes, but the datasheet says there are 24
* [https://archive.org/details/0893037893ProgrammingThe65816/page/94 Page 94] says the 65c816 has three push instructions that do not alter registers: [[PEA]], [[PEI]], and [[PER]]. But the [[stack pointer]] itself is modified. Even not counting that, there are more than three, for example [[PHA]].
* [[PLB]] is not the only instruction that modifies the [[data bank register]]; [[MVP]] and [[MVN]] do too - see section 7.18 of the 65c816 datasheet
* In the section on [[accumulator addressing]], a sentence implies that all read-modify-write instructions are unary, but [[TRB]] and [[TSB]] are not.
* [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
* [https://archive.org/details/0893037893ProgrammingThe65816/page/510 Page 510] on [[TCD]] and page 512 on [[TDC]] mentions the [[direct page register]], but this is missing from the index
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no. Many readers would find a check mark less confusing.
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The 65c02 datasheet does mention [[WAI]] and [[STP]] are supported (page 532 has them listed as unavailable)
* The [[addressing mode]] for [[WDM]] is missing, but the datasheet says it is [[Implied]]
* Assemblers are described as requiring the [[signature byte]] for [[COP]], but on the next page it says the signature byte is optional
* The page on [[PLA]] has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."
* Table 18.2 seems to imply that the [[M flag]] does not exist in [[emulation mode]] but the 65c816 datasheet says the M flag is always equal to one in emulation mode in section 2.8.

=== Quick Links ===

*[https://archive.org/details/0893037893ProgrammingThe65816/page/n7 Table of Contents]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n13 Preface]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n15 Acknowledgments]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n17 Foreword]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n19 Introduction]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n21 How to Use this Book]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n27 Part I Basics]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n29 Basic Assembly Language Programming Concepts]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n49 Part II Architecture]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n51 Architecture of the 6502]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n71 Architecture of the 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n75 Sixteen-Bit Architecture: The 65816 and the 65802]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n99 Part III Tutorial]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n101 SEP, REP, and Other Details]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n109 First Examples: Moving Data]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n133 The Simple Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n165 The Flow of Control]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n181 Built-In Arithmetic Functions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n205 Logic and Bit Manipulation Operations]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n223 The Complex Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n387 Design and Debugging]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n397 Reference]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n399 The Addressing Modes]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n447 The Instruction Sets]
<div style="column-count:10">
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n449 ADC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n451 AND]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n453 ASL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n454 BCC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n455 BCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n456 BEQ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n457 BIT]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n458 BMI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n459 BNE]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n460 BPL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n461 BRA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n462 BRK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n463 BRL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n465 BVC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n466 BVS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n467 CLC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n468 CLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n469 CLI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n470 CLV]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n471 CMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n473 COP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n475 CPX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n476 CPY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n477 DEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n478 DEX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n479 DEY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n480 EOR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n482 INC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n483 INX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n484 INY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n485 JMP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n486 JSL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n487 JSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n488 LDA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n489 LDX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n490 LDY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n491 LSR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n492 MVN]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n493 MVP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n497 ORA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n499 PEA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n500 PEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n501 PER]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n502 PHA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n503 PHB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n504 PHD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n505 PHK]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n506 PHP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n507 PHX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n508 PHY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n509 PLA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n510 PLB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n511 PLD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n512 PLP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n513 PLX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n514 PLY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n515 REP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n516 ROL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n517 ROR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n518 RTI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n520 RTL]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n522 RTS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n523 SBC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n525 SEC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n526 SED]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n527 SEI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n528 SEP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n529 STA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n530 STP]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n531 STX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n532 STY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n533 STZ]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n534 TAX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n535 TAY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n536 TCD]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n537 TCS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n538 TDC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n539 TRB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n540 TSB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n541 TSC]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n542 TSX]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n543 TXA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n544 TXS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n545 TXY]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n546 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n547 TYA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n548 WAI]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n549 WDM]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n550 XBA]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n551 XCE]
</div>
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n553 Instruction Lists]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n567 Appendices]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n569 65x Signal Description]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n577 65x Series Support Chips]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n587 The Rockwell 65C02]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n588 BBR]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n589 BBS]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n590 RMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n591 SMB]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n593 Instruction Groups]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n594 Group I Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n595 Group II Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n599 W65C816 Data Sheet]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n621 The ASCII Character Set]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n625 Index]

[[Category:ASM]]
[[Category:Books]]
[[Category:Scene Slang]]

Memory/Accumulator Select

2025-11-28T08:00:15Z

Xetheria: M flag does in fact always exist

The '''Memory/Accumulator Select''' (M) flag is bit 5 of the [[65c816]]'s [[processor status register]]. It indicates whether the [[accumulator]] is 8 or 16 bits wide:

* When clear, the accumulator is 16 bits wide. It can only be clear in [[native mode]].
* When set, the accumulator is 8 bits wide, but the high byte (B) is still retained. This is the case after reset because the processor is in [[emulation mode]].

It can be affected by:

* [[REP]] (clears it if bit 5 of operand is set)
* [[SEP]] (sets it if bit 5 of operand is set)
* [[PLP]] (pops it off the [[stack]])
* [[RTI]]

It affects the behavior of (possibly incomplete list):

* [[LDA]]
* [[STA]]
* [[STZ]]
* [[ADC]]
* [[SBC]]
* [[BIT]]
* [[CMP]]
* [[PHA]]
* [[PLA]]
* [[LSR]]
* [[ASL]]
* [[ROR]]
* [[ROL]]
* [[ORA]]
* [[AND]]
* [[EOR]]
* [[INC]]
* [[DEC]]
* [[TSB]]
* [[TRB]]

But it does not affect [[XBA]], [[TDC]], [[TCD]], [[TCS]], or [[TSC]].

There are no BMS or BMC instructions that examine this flag. [[Eyes & Lichty]] has a table which seems to imply that the M flag does not exist in [[emulation mode]][1], but the datasheet clearly states that the M flag is always equal to one in emulation mode.[2]

=== See Also ===
* [[Index Register Select]]

=== References ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422], Table 18.2. 65x Flags.
# section 2.8 "Processor Status Register (P)" of 65c816 datasheet, 2024 edition

[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

Overflow Flag

2025-11-26T03:18:58Z

Xetheria: added another definition

The '''Overflow Flag''' (V) is bit 6 of the [[status register]]. It is affected only by the following eight instructions:

* [[ADC]] (indicates signed sum overflowed)
* [[SBC]] (indicates signed difference underflowed)
* [[CLV]] (always clears it)
* [[BIT]] (becomes bit 6 or bit 14 of operand except in [[immediate addressing]])
* [[PLP]] (pulls it off the stack)
* [[RTI]] (pulls it off the stack)
* [[SEP]] (might set it)
* [[REP]] (might clear it)

Here is how it behaves:

* When the [[accumulator]] is 8 bits wide, V indicates whether the sum/difference of [[ADC]]/[[SBC]] is outside the range of -128 to 127.
* When the accumulator is 16 bits wide, V indicates whether the result of [[ADC]]/[[SBC]] is outside the range of -32768 to 32767.

In other words, the overflow flag is set when an arithmetic operation causes the most significant bit of the accumulator to change and is cleared if the bit is unchanged. Adding a positive and negative integer together never sets the overflow flag because the sum has a smaller magnitude than either addend.

It may be the most misunderstood flag of the [[65c816]] and the 6502.[2][3]

There is no [[SEV]] instruction to directly set the overflow flag, but the 6502 and 65c02 do have a hardware signal to set it. Unfortunately this hardware signal was removed on the 65c816 (or fortunately, as now it can no longer get set by accident.)

On the [[SPC700]] it can be cleared with [[CLRV]] and is set whenever the [[half-carry flag]] is set.

[[BVC]] and [[BVS]] both examine the overflow flag to decide whether or not to branch.

The overflow flag is invalid in [[decimal mode]] on the NMOS 6502, but it is valid in the 65c816's decimal mode.

=== See Also ===
* [[BVC (SPC700)]]
* [[BVS (SPC700)]]
* [[O/V]]
* [[Carry Flag]]
* [[Zero Flag]]

=== References ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/439 page 439]
# lbid, "Branching Based on the Overflow Flag" on [https://archive.org/details/0893037893ProgrammingThe65816/page/150 page 150]
# Clark, Bruce. http://www.6502.org/tutorials/vflag.html
# Shirriff, Ken. The 6502 overflow flag explained mathematically. https://www.righto.com/2012/12/the-6502-overflow-flag-explained.html
# lbid. https://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html
# Labiak, William. [https://archive.org/details/Programming_the_65816/page/n118 Page 108.]
# Pickens, John. NMOS 6502 Opcodes. http://www.6502.org/tutorials/6502opcodes.html#VFLAG
# https://forums.nesdev.org/viewtopic.php?t=6331
# Table 7-1 Caveats of 65c816 datasheet

[[Category:ASM]]
[[Category:Flags]]
[[Category:Inherited from 6502]]
[[Category:Condition Codes]]

Absolute Long Indexed, X Addressing

2025-11-25T21:51:59Z

Xetheria: replaced BBR and BBS

'''Absolute Long Indexed, X Addressing''' is supported by eight instructions:

* [[ADC]] (opcode 7F)
* [[AND]] (opcode 3F)
* [[CMP]] (opcode DF)
* [[EOR]] (opcode 5F)
* [[LDA]] (opcode BF)
* [[ORA]] (opcode 1F)
* [[SBC]] (opcode FF)
* [[STA]] (opcode 9F)

These opcodes replaced the 65c02's BBR and BBS.

==== Syntax ====
<pre>
LDA long, X
</pre>

=== See Also ===
* [[Absolute Long Addressing]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/386 page 386]
* section 3.5.6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.17

[[Category:ASM]]
[[Category:Addressing Modes]]
[[Category:Complex Admodes]]
[[Category:65c816 additions]]

dstbnk

2025-11-24T13:18:06Z

Xetheria: created page

#redirect [[Block Move Addressing]]

srcbnk

2025-11-24T13:17:36Z

Xetheria: created page

#redirect [[Block Move Addressing]]

S-CLK

2025-11-20T07:43:24Z

Xetheria: added ref

'''S-CLK''' is a clock multiplier/divider that exists only on PAL consoles.

=== Reference ===
* https://fabiensanglard.net/snes_video/index.html

[[Category:SNES Hardware]]

65c816 opcode matrix

2025-11-16T00:40:54Z

Xetheria: created page

#redirect [[65c816 Opcode Matrix]]

Processor Status Register

2025-11-07T06:26:18Z

Xetheria: clarify why STP was mentioned

The '''Processor Status Register''' (P) is on the [[65c816]] and contains several flags:

* 7: [[Negative Flag]] - N
* 6: [[Overflow Flag]] - V
* 5: [[Memory/Accumulator Select]] - M
* 4: [[Index Register Select]] - X
* 3: [[Decimal Mode]] - D
* 2: [[Interrupt Disable Flag]] - I
* 1: [[Zero Flag]] - Z
* 0: [[Carry Flag]] - C

It can be pulled from the [[stack]] via [[PLP]] and [[RTI]]. To push it to the stack, use [[PHP]]. [[COP]] and [[BRK]] also push it to the stack.

There are nine instructions that directly modify these flags, including:[3]
* [[REP]] (can clear multiple)
* [[SEP]] (can set multiple)
* [[CLC]]
* [[SEC]]
* [[CLD]]
* [[SED]]
* [[CLI]]
* [[SEI]]
* [[CLV]]

LDP does not exist, and [[STP]] does not store the register anywhere despite looking like it could stand for "store P" like other store commands.

Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are [[TCS]] and [[TXS]].

These instructions do not modify any status flags:
* [[BCC]]
* [[BCS]]
* [[BEQ]]
* [[BMI]]
* [[BNE]]
* [[BPL]]
* [[BRA]]
* [[BRL]]
* [[BVC]]
* [[BVS]]
* [[JMP]]
* [[JSL]]
* [[JSR]]
* [[MVN]]
* [[MVP]]
* [[NOP]]
* [[PEA]]
* [[PEI]]
* [[PER]]
* [[PHA]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]] ([[fullsnes]] claims the break flag is set)
* [[PHX]]
* [[PHY]]
* [[RTL]]
* [[RTS]]
* [[STA]]
* [[STP]]
* [[STX]]
* [[STY]]
* [[STZ]]
* [[TCS]]
* [[TXS]]
* [[WAI]]
* [[WDM]]

=== See Also ===
* [[Emulation Mode Flag]]
* [[Program Status Word]]
* [[DSP1 Status Register]]

=== References ===
# Table 18.2 [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422]
# Figure 17.3, Lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# lbid, Status Register Control Instructions, [https://archive.org/details/0893037893ProgrammingThe65816/page/262 page 262]
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/29 page 29]

[[Category:Registers]]
[[Category:Flags]]
[[Category:ASM]]

Derailment

2025-11-06T04:28:38Z

Xetheria: derailment became easier on SNES

'''Derailment''' is a failure state the [[65c816]] can enter. Usually as the result of a programming error, derailment from the instruction stream occurs when the CPU misinterprets an operand byte as an opcode byte or vice versa. With the SNES, derailment became easier to do than on the NES because of the existence of the [[M Flag]] and [[X Flag]], which can change the length the CPU expects some [[immediate addressing]] instructions to be, and cause catastrophic program errors if they are toggled incorrectly.

Zeroing memory can help mitigate derailment because accidentally running opcode 00h causes a [[BRK]] interrupt. To safely shut down the CPU, consider [[STP]].

=== See Also ===
* [[SEP]]
* [[REP]]

=== Reference ===
* https://forums.nesdev.org/viewtopic.php?p=104280#p104280

[[Category:ASM]]
[[Category:Scene Slang]]

PER

2025-11-05T05:08:42Z

Xetheria: self-relocatable code

Emulation Mode Flag

2025-11-05T03:42:20Z

Xetheria: why COP, BRK, and RTI take an extra cycle in native mode

The '''Emulation Mode Flag''' (E) controls whether the [[65c816]] is behaving like a 6502:
* When clear, the '816 is in '''65c816 native mode.'''
* When set, the '816 is in '''6502 emulation mode.'''

This flag cannot be modified directly and is normally hidden from the programmer. To modify it, use the [[XCE]] instruction to swap its value with the [[carry flag]]'s value. This treats the [[status register]] bits as a game of musical chairs.

The designers likely omitted CLE and SEE opcodes to set or clear it directly because dedicating two opcodes to such a rare operation is overkill.

The flag is set when a [[RESET]] interrupt is fired. In other words, the CPU always starts in emulation mode at boot and after a reset.

Emulation mode is not perfect. Some important behavior differences from the 6502 are:
* The 65c816 does not attempt to emulate the illegal 6502 opcodes because its [[65c816 Opcode Matrix|opcode matrix]] is already full. All 256 opcodes work in both native and emulation mode, but many are less useful in emulation mode.[3]
* The [[direct page]] is fully relocatable in both native and emulation mode even though it doesn't exist on the 6502, so pointing it to the zero page right before running 6502 code is advised to ensure maximum compatibility
* Direct page indexed addressing will always wrap around and remain within the direct page in emulation mode, instead of possibly crossing over into the next page. ([[E&L]], [https://archive.org/details/0893037893ProgrammingThe65816/page/374 page 374])
* The [[program bank register]] and [[data bank register]] still exist in emulation mode even though they don't exist on a 6502, so memory accesses may not always access bank zero.
* the hidden [[B accumulator]] still exists in emulation mode even though it does not on a 6502

For writing new SNES code it is recommended to almost always stay in native mode even if dealing with 8 bit data. Some reasons are:
* Page boundary crossings incur a one cycle penalty in emulation mode. Emulation mode emulates the NMOS 6502 cycle counts.
* Large amounts of 8-bit data can sometimes be processed in 16-bit chunks, and doing so can take fewer loads/stores/transfers than treating them as 8-bit.
* The [[break flag]] need not be examined in native mode because there are more interrupt vectors. (In fact, it does not even exist).

On the other hand, [[COP]], [[BRK]], and [[RTI]] take one extra cycle in native mode because of the [[bank]] number. For running 6502 code with minimal issues it is still recommended to use emulation mode. For example, one quirk of 8-bit native mode is that [[TXS]] points the [[stack]] to the [[zeropage]].

Emulation code need not be in [[bank]] 0.

In emulation mode, the [[stack pointer]]'s high byte is always one. The M and X flags are always set in emulation mode.[4]

=== See Also ===
* [[SA-1]]

=== References ===
# Figure 17.3, [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#APPENDIX
# section 7.8 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.8, lbid.

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

WDM

2025-11-04T07:27:25Z

Xetheria: note about breakpoints

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Implied]] (type 3)[4]
|42
|2 bytes
|2 cycles
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[N Flag|N]]
|[[V Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Z Flag|Z]]
|[[C Flag|C]]
|+
|.
|.
|.
|.
|.
|.
|.
|.
|}

'''WDM''' (the initials of [https://themenschfoundation.org/who-is-william-d-mensch-jr-aka-bill-mensch/ William David Mensch], the designer of the [[65c816]]) is an instruction that reserves its [[signature byte]] for future expansion of the instruction set. None of these extra 256 opcodes were ever implemented, so WDM functions essentially as a two-byte [[NOP]].

No flags are affected, but future expanded WDM opcodes may affect the flags (or even have different instruction lengths/speeds for that matter.)

WDM "works" even in [[emulation mode]].

==== Syntax ====
<pre>
WDM
WDM sig
</pre>

ca65 for example requires the signature byte to be specified in the assembly source.

Directly specifying the opcode 42h can be used to skip the next instruction.[5]

WDM is a popular way to insert debug breakpoints into SNES code - by configuring your emulator to trip on WDM, the signature byte can be used to disambiguate which breakpoint has been reached.

=== Trivia ===
* WDM is the only [[implied addressing]] instruction that is more than one byte long
* The [[Labiak]] textbook does not describe the WDM instruction.

=== See Also ===
* [[COP]]
* [[BRK]]

=== External Links ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/523 page 523] on WDM
# snes9x implementation of WDM: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L3335
# undisbeliever on WDM: https://undisbeliever.net/snesdev/65816-opcodes.html#wdm-reserved-for-future-expansion
# Table 5-4 Opcode Matrix of official 65c816 datasheet
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.7

[[Category: ASM]]
[[Category:65c816 additions]]
[[Category:Two-byte Instructions]]
[[Category:Implied Instructions]]
[[Category:Two-cycle Instructions]]

Emulation Mode Flag

2025-10-29T21:36:57Z

Xetheria: mentioned TXS quirk

The '''Emulation Mode Flag''' (E) controls whether the [[65c816]] is behaving like a 6502:
* When clear, the '816 is in '''65c816 native mode.'''
* When set, the '816 is in '''6502 emulation mode.'''

This flag cannot be modified directly and is normally hidden from the programmer. To modify it, use the [[XCE]] instruction to swap its value with the [[carry flag]]'s value. This treats the [[status register]] bits as a game of musical chairs.

The designers likely omitted CLE and SEE opcodes to set or clear it directly because dedicating two opcodes to such a rare operation is overkill.

The flag is set when a [[RESET]] interrupt is fired. In other words, the CPU always starts in emulation mode at boot and after a reset.

Emulation mode is not perfect. Some important behavior differences from the 6502 are:
* The 65c816 does not attempt to emulate the illegal 6502 opcodes because its [[65c816 Opcode Matrix|opcode matrix]] is already full. All 256 opcodes work in both native and emulation mode, but many are less useful in emulation mode.[3]
* The [[direct page]] is fully relocatable in both native and emulation mode even though it doesn't exist on the 6502, so pointing it to the zero page right before running 6502 code is advised to ensure maximum compatibility
* Direct page indexed addressing will always wrap around and remain within the direct page in emulation mode, instead of possibly crossing over into the next page. ([[E&L]], [https://archive.org/details/0893037893ProgrammingThe65816/page/374 page 374])
* The [[program bank register]] and [[data bank register]] still exist in emulation mode even though they don't exist on a 6502, so memory accesses may not always access bank zero.
* the hidden [[B accumulator]] still exists in emulation mode even though it does not on a 6502

For writing new SNES code it is recommended to almost always stay in native mode even if dealing with 8 bit data. Some reasons are:
* Page boundary crossings incur a one cycle penalty in emulation mode. Emulation mode emulates the NMOS 6502 cycle counts.
* Large amounts of 8-bit data can sometimes be processed in 16-bit chunks, and doing so can take fewer loads/stores/transfers than treating them as 8-bit.
* The [[break flag]] need not be examined in native mode because there are more interrupt vectors. (In fact, it does not even exist).

On the other hand, [[COP]], [[BRK]], and [[RTI]] take one extra cycle in native mode. For running 6502 code with minimal issues it is still recommended to use emulation mode. For example, one quirk of 8-bit native mode is that [[TXS]] points the [[stack]] to the [[zeropage]].

Emulation code need not be in [[bank]] 0.

In emulation mode, the [[stack pointer]]'s high byte is always one. The M and X flags are always set in emulation mode.[4]

=== See Also ===
* [[SA-1]]

=== References ===
# Figure 17.3, [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#APPENDIX
# section 7.8 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.8, lbid.

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

Overflow Flag

2025-10-28T22:49:22Z

Xetheria: /* References */ cleaner URLs

The '''Overflow Flag''' (V) is bit 6 of the [[status register]]. It is affected only by the following eight instructions:

* [[ADC]] (indicates signed sum overflowed)
* [[SBC]] (indicates signed difference underflowed)
* [[CLV]] (always clears it)
* [[BIT]] (becomes bit 6 or bit 14 of operand except in [[immediate addressing]])
* [[PLP]] (pulls it off the stack)
* [[RTI]] (pulls it off the stack)
* [[SEP]] (might set it)
* [[REP]] (might clear it)

Here is how it behaves:

* When the [[accumulator]] is 8 bits wide, V indicates whether the sum/difference of [[ADC]]/[[SBC]] is outside the range of -128 to 127.
* When the accumulator is 16 bits wide, V indicates whether the result of [[ADC]]/[[SBC]] is outside the range of -32768 to 32767.

Adding a positive and negative integer together never sets the overflow flag because the sum has a smaller magnitude than either addend.

It may be the most misunderstood flag of the [[65c816]] and the 6502.[2][3]

There is no [[SEV]] instruction to directly set the overflow flag, but the 6502 and 65c02 do have a hardware signal to set it. Unfortunately this hardware signal was removed on the 65c816 (or fortunately, as now it can no longer get set by accident.)

On the [[SPC700]] it can be cleared with [[CLRV]] and is set whenever the [[half-carry flag]] is set.

[[BVC]] and [[BVS]] both examine the overflow flag to decide whether or not to branch.

The overflow flag is invalid in [[decimal mode]] on the NMOS 6502, but it is valid in the 65c816's decimal mode.

=== See Also ===
* [[BVC (SPC700)]]
* [[BVS (SPC700)]]
* [[O/V]]
* [[Carry Flag]]
* [[Zero Flag]]

=== References ===
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/439 page 439]
# lbid, "Branching Based on the Overflow Flag" on [https://archive.org/details/0893037893ProgrammingThe65816/page/150 page 150]
# Clark, Bruce. http://www.6502.org/tutorials/vflag.html
# Shirriff, Ken. The 6502 overflow flag explained mathematically. https://www.righto.com/2012/12/the-6502-overflow-flag-explained.html
# lbid. https://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html
# Labiak, William. [https://archive.org/details/Programming_the_65816/page/n118 Page 108.]
# Pickens, John. NMOS 6502 Opcodes. http://www.6502.org/tutorials/6502opcodes.html#VFLAG
# https://forums.nesdev.org/viewtopic.php?t=6331
# Table 7-1 Caveats of 65c816 datasheet

[[Category:ASM]]
[[Category:Flags]]
[[Category:Inherited from 6502]]
[[Category:Condition Codes]]

XBA

2025-10-28T22:36:25Z

Xetheria: /* Syntax */ probably doesn't use register renaming

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Implied]] (type 1)
|EB
|1 byte
|3 cycles
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''XBA''' is a [[65c816]] instruction that exchanges the values of the high byte (B) and low byte (typically called A) of the [[C accumulator]]. It works even in [[6502 emulation mode]]. In [[65816 native mode]], its standard mnemonic is still "XBA" even when the accumulator is 16-bits wide. An alternative mnemonic is "SWA."

XBA can be used to convert [[big endian]] data to [[little endian]] and vice versa. XBA appears to be the only direct way to access the high B byte when the [[M flag]] is set without losing any register values, with [[TCD]], [[TCS]], [[TAX]], and [[TAY]]
providing less direct access.

The [[negative flag]] will match the most significant bit of the new low byte (A) of the accumulator.
The [[zero flag]] will be set if and only if the new low byte (A) of the accumulator is zero, otherwise it is cleared. In other words, XBA ignores the M flag.

==== Syntax ====
<pre>
XBA
SWA
</pre>

Even though the hidden B byte is colloquially considered to be a second, more limited accumulator, XBA still isn't considered to use [[accumulator addressing]]. As of 2025 it is unknown whether XBA uses register renaming, but it would be surprising if it did because it should only take two cycles to flip a flip-flop.

[[File:xba.png]]

=== See Also ===
* [[XCE]]
* [[XCN]]
* [[SWAP]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/524 page 524] on XBA
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n214 page 204] on XBA
* snes9x implementation of XBA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L3261
* undisbeliever on XBA: https://undisbeliever.net/snesdev/65816-opcodes.html#xba-exchange-the-b-and-a-accumulators
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.10.3

[[Category:ASM]]
[[Category:65c816 additions]]
[[Category:Exchange Instructions]]
[[Category:One-byte Instructions]]
[[Category:Implied Instructions]]
[[Category:Three-cycle Instructions]]
[[Category:Single Admode Mnemonics]]

Emulation Mode Flag

2025-10-28T18:51:28Z

Xetheria: clarify that memory accesses may not always access bank 0

The '''Emulation Mode Flag''' (E) controls whether the [[65c816]] is behaving like a 6502:
* When clear, the '816 is in '''65c816 native mode.'''
* When set, the '816 is in '''6502 emulation mode.'''

This flag cannot be modified directly and is normally hidden from the programmer. To modify it, use the [[XCE]] instruction to swap its value with the [[carry flag]]'s value. This treats the [[status register]] bits as a game of musical chairs.

The designers likely omitted CLE and SEE opcodes to set or clear it directly because dedicating two opcodes to such a rare operation is overkill.

The flag is set when a [[RESET]] interrupt is fired. In other words, the CPU always starts in emulation mode at boot and after a reset.

Emulation mode is not perfect. Some important behavior differences from the 6502 are:
* The 65c816 does not attempt to emulate the illegal 6502 opcodes because its [[65c816 Opcode Matrix|opcode matrix]] is already full. All 256 opcodes work in both native and emulation mode, but many are less useful in emulation mode.[3]
* The [[direct page]] is fully relocatable in both native and emulation mode even though it doesn't exist on the 6502, so pointing it to the zero page right before running 6502 code is advised to ensure maximum compatibility
* Direct page indexed addressing will always wrap around and remain within the direct page in emulation mode, instead of possibly crossing over into the next page. ([[E&L]], [https://archive.org/details/0893037893ProgrammingThe65816/page/374 page 374])
* The [[program bank register]] and [[data bank register]] still exist in emulation mode even though they don't exist on a 6502, so memory accesses may not always access bank zero.
* the hidden [[B accumulator]] still exists in emulation mode even though it does not on a 6502

For writing new SNES code it is recommended to almost always stay in native mode even if dealing with 8 bit data. Some reasons are:
* Page boundary crossings incur a one cycle penalty in emulation mode. Emulation mode emulates the NMOS 6502 cycle counts.
* Large amounts of 8-bit data can sometimes be processed in 16-bit chunks, and doing so can take fewer loads/stores/transfers than treating them as 8-bit.
* The [[break flag]] need not be examined in native mode because there are more interrupt vectors. (In fact, it does not even exist).

On the other hand, [[COP]], [[BRK]], and [[RTI]] take one extra cycle in native mode.

Emulation code need not be in [[bank]] 0.

In emulation mode, the [[stack pointer]]'s high byte is always one. The M and X flags are always set in emulation mode.[4]

=== See Also ===
* [[SA-1]]

=== References ===
# Figure 17.3, [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#APPENDIX
# section 7.8 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.8, lbid.

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

Bank Address Register

2025-10-28T18:49:32Z

Xetheria: works even in emulation mode

''Note: this page is likely inaccurate/confusing;''

The '''Bank Address Register''' (also known as the '''bank byte''') is Nintendo's name for the 8-bit register that fills in the most significant bits of a 24-bit address memory access by the [[5A22]]. It keeps track of what [[bank]] the CPU is configured to use. It is cleared to zero on reset.[2]

WDC calls this register the '''Data Bank Register''' (DBR). Even in [[emulation mode]], DBR still exists and tells the '816 which bank to use.

[[PLB]], [[MVN]], and [[MVP]] modify this register. [[PHB]] pushes it onto the [[stack]]. [[TSB]] does not transfer the [[stack pointer]] to the DBR despite appearing like a transfer mnemonic.

=== See Also ===
* [[Program Bank Register]]
* [[Address Bus A]]

=== References ===
# Figure 2-21-2 on [https://archive.org/details/SNESDevManual/book1/page/n94 page 2-21-3 of Book I] of the official Super Nintendo development manual
# section 2.5 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53]
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/55 page 55]
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/114 page 114]

[[Category:Registers]]
[[Category:ASM]]
[[Category:Bank Registers]]

Emulation Mode Flag

2025-10-28T18:35:28Z

Xetheria: linkify page 374

The '''Emulation Mode Flag''' (E) controls whether the [[65c816]] is behaving like a 6502:
* When clear, the '816 is in '''65c816 native mode.'''
* When set, the '816 is in '''6502 emulation mode.'''

This flag cannot be modified directly and is normally hidden from the programmer. To modify it, use the [[XCE]] instruction to swap its value with the [[carry flag]]'s value. This treats the [[status register]] bits as a game of musical chairs.

The designers likely omitted CLE and SEE opcodes to set or clear it directly because dedicating two opcodes to such a rare operation is overkill.

The flag is set when a [[RESET]] interrupt is fired. In other words, the CPU always starts in emulation mode at boot and after a reset.

Emulation mode is not perfect. Some important behavior differences from the 6502 are:
* The 65c816 does not attempt to emulate the illegal 6502 opcodes because its [[65c816 Opcode Matrix|opcode matrix]] is already full. All 256 opcodes work in both native and emulation mode, but many are less useful in emulation mode.[3]
* The [[direct page]] is fully relocatable in both native and emulation mode even though it doesn't exist on the 6502, so pointing it to the zero page right before running 6502 code is advised to ensure maximum compatibility
* Direct page indexed addressing will always wrap around and remain within the direct page in emulation mode, instead of possibly crossing over into the next page. ([[E&L]], [https://archive.org/details/0893037893ProgrammingThe65816/page/374 page 374])
* The [[program bank register]] and [[data bank register]] still exist in emulation mode even though they don't exist on a 6502
* the hidden [[B accumulator]] still exists in emulation mode even though it does not on a 6502

For writing new SNES code it is recommended to almost always stay in native mode even if dealing with 8 bit data. Some reasons are:
* Page boundary crossings incur a one cycle penalty in emulation mode. Emulation mode emulates the NMOS 6502 cycle counts.
* Large amounts of 8-bit data can sometimes be processed in 16-bit chunks, and doing so can take fewer loads/stores/transfers than treating them as 8-bit.
* The [[break flag]] need not be examined in native mode because there are more interrupt vectors. (In fact, it does not even exist).

On the other hand, [[COP]], [[BRK]], and [[RTI]] take one extra cycle in native mode.

Emulation code need not be in [[bank]] 0.

In emulation mode, the [[stack pointer]]'s high byte is always one. The M and X flags are always set in emulation mode.[4]

=== See Also ===
* [[SA-1]]

=== References ===
# Figure 17.3, [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#APPENDIX
# section 7.8 of 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
# section 2.8, lbid.

[[Category:SNES Hardware]]
[[Category:ASM]]
[[Category:Flags]]
[[Category:65c816 additions]]

TCS

2025-10-28T18:07:57Z

Xetheria: ignores M flag

XBA

2025-10-28T17:53:45Z

Xetheria: XBA ignores M flag, clarified that other instructions overwrite regs

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Implied]] (type 1)
|EB
|1 byte
|3 cycles
|}

{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="8"|Flags Affected
|+
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]]
|[[Decimal Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|N
|.
|.
|.
|.
|.
|Z
|.
|}

'''XBA''' is a [[65c816]] instruction that exchanges the values of the high byte (B) and low byte (typically called A) of the [[C accumulator]]. It works even in [[6502 emulation mode]]. In [[65816 native mode]], its standard mnemonic is still "XBA" even when the accumulator is 16-bits wide. An alternative mnemonic is "SWA."

XBA can be used to convert [[big endian]] data to [[little endian]] and vice versa. XBA appears to be the only direct way to access the high B byte when the [[M flag]] is set without losing any register values, with [[TCD]], [[TCS]], [[TAX]], and [[TAY]]
providing less direct access.

The [[negative flag]] will match the most significant bit of the new low byte (A) of the accumulator.
The [[zero flag]] will be set if and only if the new low byte (A) of the accumulator is zero, otherwise it is cleared. In other words, XBA ignores the M flag.

==== Syntax ====
<pre>
XBA
SWA
</pre>

Even though the hidden B byte is colloquially considered to be a second, more limited accumulator, XBA still isn't considered to use [[accumulator addressing]]. As of 2025 it is unknown whether XBA is implemented with register renaming.

[[File:xba.png]]

=== See Also ===
* [[XCE]]
* [[XCN]]
* [[SWAP]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/524 page 524] on XBA
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n214 page 204] on XBA
* snes9x implementation of XBA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L3261
* undisbeliever on XBA: https://undisbeliever.net/snesdev/65816-opcodes.html#xba-exchange-the-b-and-a-accumulators
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.10.3

[[Category:ASM]]
[[Category:65c816 additions]]
[[Category:Exchange Instructions]]
[[Category:One-byte Instructions]]
[[Category:Implied Instructions]]
[[Category:Three-cycle Instructions]]
[[Category:Single Admode Mnemonics]]

Direct Page Indexed Indirect, X Addressing

2025-10-28T02:27:33Z

Xetheria: /* References */ hid archive URL

'''Direct Page Indexed Indirect, X Addressing''' is supported by eight instructions:

* [[ADC]] (opcode 61)
* [[AND]] (opcode 21)
* [[CMP]] (opcode C1)
* [[EOR]] (opcode 41)
* [[LDA]] (opcode A1)
* [[ORA]] (opcode 01)
* [[SBC]] (opcode E1)
* [[STA]] (opcode 81)

==== Syntax ====
<pre>
LDA (dp, X)
</pre>

==== See Also ====
* [[Direct Page Indirect Addressing]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/392 page 392]
* section 3.5.10 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:ASM]]
[[Category:65c816 additions]]
[[Category:Complex Admodes]]
[[Category:Addressing Modes]]

Direct Page Indirect Addressing

2025-10-28T02:04:33Z

Xetheria: /* Syntax */ meaning

'''Direct Page Indirect Addressing''' is supported by eight instructions:

* [[ADC]] (opcode 72)
* [[AND]] (opcode 32)
* [[CMP]] (opcode D2)
* [[EOR]] (opcode 52)
* [[LDA]] (opcode B2)
* [[ORA]] (opcode 12)
* [[SBC]] (opcode F2)
* [[STA]] (opcode 92)

==== Syntax ====
<pre>
LDA (dp)
</pre>

In the above example, the 16-bit address stored at location dp of the direct page is fetched, and then the accumulator is loaded with the byte that lives at that address.

=== See Also ===
* [[Direct Page Indirect Long Addressing]]
* [[Direct Page Addressing]]

=== References ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/393 page 393]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/128 page 128], lbid
* section 3.5.16 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf

[[Category:Addressing Modes]]
[[Category:Simple Admodes]]
[[Category:ASM]]
[[Category:65c816 additions]]

BRK

2025-10-28T00:59:14Z

Xetheria: NMOS 6502 BRK did not affect decimal flag

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Length'''
|'''Speed'''
|+
|[[Stack Addressing|Stack]] (Interrupt)
|00
|2 bytes
|8 cycles*
|}

{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="9"|Flags Affected
|+
|
|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[M Flag|M]]
|[[X Flag|X]] / [[Break Flag|B]]
|[[D Flag|D]]
|[[I Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
|+
|[[65c816 native mode]]
|.
|.
|.
|.
|0
|1
|.
|.
|+
|[[6502 emulation mode]]
|.
|.
|.
|1
|0
|1
|.
|.
|}

'''BRK''' (Break) is a 65x instruction that triggers a non-maskable software interrupt ([[Non-Maskable Interrupt|NMI]]). The byte following the opcode is called the [[signature byte]]. The state of the [[interrupt disable flag]] has no effect on the behavior of BRK although it will be set after BRK runs.

In [[native mode]] the [[program bank register]] is pushed to the [[stack]]. Then the [[program counter]] is incremented by two and then pushed to the stack. Then the [[status register]] (with the [[break flag]] set, if in emulation mode) is pushed to the stack. Then the interrupt disable flag is set. In native mode, the program bank register is then cleared.

Control is routed to the BRK handler, whose address is stored at the BRK vector:
* In native mode, this vector is at $00:FFE6.
* In emulation mode, this vector is at $FFFE.

==== Syntax ====
<pre>
BRK
BRK sig
</pre>

==== Cycle Skipped ====
BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].

If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction. In this case the [[interrupt handler]] must decrement the [[return address]] on the [[stack]] so that the eventual [[RTI]] does not cause [[derailment]].

[[File:brk.png]]

BRK used to be considered a one-byte instruction in an early datasheet. On the NMOS 6502, BRK does not affect the decimal flag, but this likely only affects porting code from systems other than the NES because the NES does not have decimal mode anyway.

=== See Also ===
* [[RTI]]
* [[BRK (SPC700)]]
* [[NMI]]
* [[IRQ]]
* [[COP]]
* [[WDM]]
* [[CLD]]
* [[SEI]]

=== External Links ===
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/436 page 436] on BRK
* Figure 13.3, Break Signature Byte Illustration, lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n136 page 126] on BRK
* 9.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n164 page 144] on BRK
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n265 page 252] on BRK
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n98 page 3-49] on BRK
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BRK
* Clark, Bruce. http://www.6502.org/tutorials/65c02opcodes.html#6
* https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts

[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Two-byte Instructions]]
[[Category:Single Admode Mnemonics]]

Carry Flag

2025-10-25T21:54:49Z

Xetheria: CMP, CPX, CPY set if no borrow required

The '''Carry Flag''' (C) is bit 0 of the [[65c816]]'s [[status register]].

It can be set with [[SEC]] and cleared with [[CLC]]. Or, [[SEP]] and [[REP]] can be used.

The following other 10 instructions have side effects that directly affect the carry flag, which includes all arithmetic instructions (except those that can only increment/decrement by one) and all shift/rotate instructions:

* [[ADC]] (becomes set when an addition overflows)
* [[ASL]] (becomes whatever the most significant bit was)
* [[CMP]] (set if no borrow required, cleared otherwise)
* [[CPX]] (set if no borrow required, cleared otherwise)
* [[CPY]] (set if no borrow required, cleared otherwise)
* [[LSR]] (becomes whatever bit 0 was)
* [[ROL]] (becomes whatever the most significant bit was)
* [[ROR]] (becomes whatever bit 0 was)
* [[SBC]] (where it is often called the "borrow flag" instead)
* [[XCE]] (becomes whatever the e flag was)

The following two instructions indirectly affect the carry flag by loading the [[status register]]:

* [[PLP]]
* [[RTI]]

The carry flag influences whether [[BCS]] and [[BCC]] branch or not.

As mentioned above, none of [[INC]], [[DEC]], [[INX]], [[DEX]], [[INY]] nor [[DEY]] modify the carry flag.

=== See Also ===
* [[CY]], the [[Super FX]]'s carry flag
* [[Negative Flag]]
* [[Overflow Flag]]

=== References ===
* Labiak, William. [https://archive.org/details/Programming_the_65816/page/n118 Page 108.]
* [[Eyes & Lichty]], "Branching Based on the Carry Flag" on [https://archive.org/details/0893037893ProgrammingThe65816/page/147 page 147]

[[Category:ASM]]
[[Category:Flags]]
[[Category:Inherited from 6502]]
[[Category:Condition Codes]]

Control Deck

2025-10-25T20:21:32Z

Xetheria: official jargon

The '''Control Deck''' is the main console device, containing the [[SNES Motherboard]] and having an [[ABS|ABS plastic]] shell exterior.

It has part numbers 22945 (SNS) and 21712 (SFX).

[[Category:SNES Hardware]]
[[Category:Official Jargon]]