SnesLab - Recent changes [en]

TSB

Xetheria — Wed, 06 May 2026 08:21:12 GMT

clarify second operation

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	'''TSB''' (Test and Set Bits) is a [[65c816]] instruction that tests and sets bits using the [[accumulator]]. For each set bit of the accumulator, TSB sets the corresponding memory bit. All other memory bits are left unchanged.		'''TSB''' (Test and Set Bits) is a [[65c816]] instruction that tests and sets bits using the [[accumulator]]. For each set bit of the accumulator, TSB sets the corresponding memory bit. All other memory bits are left unchanged.

	TSB performs a logical AND (conjunction) and the [[zero flag]] ~~is set or cleared~~ to reflect whether the conjunction is zero. The conjunction itself is discarded.		Also, TSB performs a logical AND (conjunction) between the accumulator and memory values, setting or clearing the [[zero flag]] to reflect whether the conjunction is zero. The conjunction itself is discarded.

	The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

TRB

Xetheria — Wed, 06 May 2026 08:17:24 GMT

clarify

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	'''TRB''' (Test and Reset Bits) is a [[65c816]] instruction that tests and resets bits using the [[accumulator]]. For each set bit in the accumulator, TRB clears the corresponding memory bit. All other memory bits are unchanged.		'''TRB''' (Test and Reset Bits) is a [[65c816]] instruction that tests and resets bits using the [[accumulator]]. For each set bit in the accumulator, TRB clears the corresponding memory bit. All other memory bits are unchanged.

	TRB performs a logical AND (conjunction) and the [[zero flag]] ~~is set or cleared~~ to reflect whether the conjunction is zero. The conjunction itself is discarded.		Also, TRB performs a logical AND (conjunction) between the accumulator and memory values, setting or clearing the [[zero flag]] to reflect whether the conjunction is zero. The conjunction itself is discarded.

	The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

TSB

Xetheria — Wed, 06 May 2026 08:07:53 GMT

all other memory bits left unchanged

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	'''TSB''' (Test and Set Bits) is a [[65c816]] instruction that tests and sets bits using the [[accumulator]]. For each set bit of the accumulator, TSB sets the corresponding memory bit.		'''TSB''' (Test and Set Bits) is a [[65c816]] instruction that tests and sets bits using the [[accumulator]]. For each set bit of the accumulator, TSB sets the corresponding memory bit. All other memory bits are left unchanged.

	TSB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.		TSB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.

TRB

Xetheria — Wed, 06 May 2026 08:06:41 GMT

all other memory bits unchanged

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	'''TRB''' (Test and Reset Bits) is a [[65c816]] instruction that tests and resets bits using the [[accumulator]]. For each set bit in the accumulator, TRB clears the corresponding memory bit.		'''TRB''' (Test and Reset Bits) is a [[65c816]] instruction that tests and resets bits using the [[accumulator]]. For each set bit in the accumulator, TRB clears the corresponding memory bit. All other memory bits are unchanged.

	TRB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.		TRB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.

TSB

Xetheria — Wed, 06 May 2026 07:36:14 GMT

effective address plus one

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	TSB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.		TSB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.

			The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

TRB

Xetheria — Wed, 06 May 2026 07:35:55 GMT

effective address plus one

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	TRB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.		TRB performs a logical AND (conjunction) and the [[zero flag]] is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.

			The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit, the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

STZ

Xetheria — Wed, 06 May 2026 07:34:11 GMT

effective address plus one

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	'''STZ''' (Store Zero) is a [[65c816]] instruction that zeros out memory. The size of the [[accumulator]] determines how many zero bytes are written.		'''STZ''' (Store Zero) is a [[65c816]] instruction that zeros out memory. The size of the [[accumulator]] determines how many zero bytes are written. If 16-bit, the second zero is written to the effective address plus one.

	STZ has the same effect as [[STA]] when the accumulator is zero. It was not available on the original NMOS 6502 and was probably added to the CMOS version in order to make code faster/smaller because zero is such a common value to store.		STZ has the same effect as [[STA]] when the accumulator is zero. It was not available on the original NMOS 6502 and was probably added to the CMOS version in order to make code faster/smaller because zero is such a common value to store.

SBC

Xetheria — Wed, 06 May 2026 07:31:58 GMT

effective address plus one

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	If the [[carry flag]] (aka borrow flag) is clear, one more is subtracted. As there is no subtract-without-carry instruction, [[SEC]] should be run beforehand or the carry flag should otherwise be ensured to be set, otherwise the difference may be one greater than expected.		If the [[carry flag]] (aka borrow flag) is clear, one more is subtracted. As there is no subtract-without-carry instruction, [[SEC]] should be run beforehand or the carry flag should otherwise be ensured to be set, otherwise the difference may be one greater than expected.

	If the ~~difference~~ is ~~negative,~~ the ~~carry flag will be cleared, otherwise it will be set~~.		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	If the [[decimal flag]] is set, then [[binary coded decimal]] subtraction is performed, otherwise binary subtraction.		If the difference is negative, the carry flag will be cleared, otherwise it will be set. If the [[decimal flag]] is set, then [[binary coded decimal]] subtraction is performed, otherwise binary subtraction.

	==== Syntax ====		==== Syntax ====

ADC

Xetheria — Wed, 06 May 2026 07:29:22 GMT

accumulator -> immediate addressing

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	'''ADC''' (Add with Carry) is the main 65x addition instruction. The accumulator is always both one of the addends and where the sum is stored. The operand serves as the other addend. The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[~~accumulator~~ addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		'''ADC''' (Add with Carry) is the main 65x addition instruction. The accumulator is always both one of the addends and where the sum is stored. The operand serves as the other addend. The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	As there is no add-without-carry instruction, a [[CLC]] should be run (or the carry flag otherwise ensured to be clear) before an ADC, or else the sum will be one greater than expected.		As there is no add-without-carry instruction, a [[CLC]] should be run (or the carry flag otherwise ensured to be clear) before an ADC, or else the sum will be one greater than expected.

ROR

Xetheria — Wed, 06 May 2026 07:27:55 GMT

effective address plus one

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	* When the [[accumulator]] is 8 bits wide, 9 bits are rotated.		* When the [[accumulator]] is 8 bits wide, 9 bits are rotated.
	* When the accumulator is 16 bits wide, 17 bits are rotated.		* When the accumulator is 16 bits wide, 17 bits are rotated. If not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

ROL

Xetheria — Wed, 06 May 2026 07:27:09 GMT

effective address plus one

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	* When the [[accumulator]] is 8 bits wide, 9 bits are rotated.		* When the [[accumulator]] is 8 bits wide, 9 bits are rotated.
	* When the accumulator is 16 bits wide, 17 bits are rotated.		* When the accumulator is 16 bits wide, 17 bits are rotated. If not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

PLY

Xetheria — Wed, 06 May 2026 07:25:19 GMT

if 16-bit operation

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	'''PLY''' (PulL Y) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[Y index register]]. PLY increments the [[stack pointer]] before the pull.		'''PLY''' (PulL Y) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[Y index register]]. PLY increments the [[stack pointer]] before the pull. If Y is 16 bits wide, the low order byte is pulled first.

	==== Syntax ====		==== Syntax ====

PLX

Xetheria — Wed, 06 May 2026 07:24:21 GMT

if 16-bit operation

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	'''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX increments the [[stack pointer]] before the pull.		'''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX increments the [[stack pointer]] before the pull. If X is 16 bits wide, the low order byte is pulled first.

	The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the [[zero flag]].		The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the [[zero flag]].

ORA

Xetheria — Wed, 06 May 2026 07:18:57 GMT

effective address plus one

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	'''ORA''' is a 65x instruction that performs a logical OR between the datum at the effective address and the [[accumulator]] and stores the disjunction in the accumulator. The size of the accumulator determines whether 8 or 16 bits are ORed together with it.		'''ORA''' is a 65x instruction that performs a logical OR between the datum at the effective address and the [[accumulator]] and stores the disjunction in the accumulator. The size of the accumulator determines whether 8 or 16 bits are ORed together with it. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

LSR

Xetheria — Wed, 06 May 2026 07:15:50 GMT

effective address plus one

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	'''LSR''' (Logical Shift Right) is a 65x instruction that shifts every bit of a value one bit to the right (division by two). The most significant bit and [[negative flag]] are cleared. The least significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROR]]).		'''LSR''' (Logical Shift Right) is a 65x instruction that shifts every bit of a value one bit to the right (division by two). The most significant bit and [[negative flag]] are cleared. The least significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROR]]).

	The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag.		The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

LDY

Xetheria — Wed, 06 May 2026 07:13:49 GMT

effective address plus one

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	'''LDY''' (Load Y) is a 65x instruction that loads a value into the [[Y index register]]. In [[immediate addressing]] only, LDY takes a total of 3 bytes when the index registers are 16 bits wide.		'''LDY''' (Load Y) is a 65x instruction that loads a value into the [[Y index register]]. The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

			In [[immediate addressing]] only, LDY takes a total of 3 bytes when the index registers are 16 bits wide.

	==== Syntax ====		==== Syntax ====

LDX

Xetheria — Wed, 06 May 2026 07:12:03 GMT

effective address plus one

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	'''LDX''' (Load X) is a 65x instruction that loads a value into the [[X index register]]. In [[immediate addressing]] only, LDX is a total of 3 bytes long when the index registers are 16 bits wide.		'''LDX''' (Load X) is a 65x instruction that loads a value into the [[X index register]]. The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

			In [[immediate addressing]] only, LDX is a total of 3 bytes long when the index registers are 16 bits wide.

	==== Syntax ====		==== Syntax ====

LDA

Xetheria — Wed, 06 May 2026 07:07:54 GMT

effective address plus one

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	'''LDA''' (LoaD Accumulator) is a 65x instruction that loads a value into the accumulator. In [[immediate addressing]] only, LDA is a total of 3 bytes long when the accumulator is 16 bits wide.		'''LDA''' (LoaD Accumulator) is a 65x instruction that loads a value into the accumulator. The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

			In [[immediate addressing]] only, LDA is a total of 3 bytes long when the accumulator is 16 bits wide.

	==== Syntax ====		==== Syntax ====

AND

Xetheria — Wed, 06 May 2026 07:05:36 GMT

accumulator -> immediate addressing

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	'''AND''' is a 65x instruction that performs a logical AND. The conjunction is stored in the [[accumulator]]. The size of the accumulator determines how much data is ANDed: if 16-bit and not using [[~~accumulator~~ addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		'''AND''' is a 65x instruction that performs a logical AND. The conjunction is stored in the [[accumulator]]. The size of the accumulator determines how much data is ANDed: if 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

EOR

Xetheria — Wed, 06 May 2026 07:05:02 GMT

accumulator -> immediate addressing

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	'''EOR''' is a 65x instruction that performs a bitwise [https://mathworld.wolfram.com/XOR.html exclusive or] between its operand and the accumulator. The sum is stored in the [[accumulator]]. The size of the accumulator determines whether 8 or 16 bits are EORed together with it.		'''EOR''' is a 65x instruction that performs a bitwise [https://mathworld.wolfram.com/XOR.html exclusive or] between its operand and the accumulator. The sum is stored in the [[accumulator]]. The size of the accumulator determines whether 8 or 16 bits are EORed together with it. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

CPY

Xetheria — Wed, 06 May 2026 07:01:48 GMT

effective address plus one

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	'''CPY''' (Compare Y) is a 65x instruction that compares the value of the [[Y index register]] to something. Internally, this is done via a subtraction, but the difference is not stored anywhere. Thus, the purpose of CPY is to setup the flags. The index register Y is the minuend. Depending on the addressing mode used, the subtrahend will be either an immediate value or the value stored at the effective address specified by the operand. The contents at the effective address (when not using immediate data) and the Y index register both remain unchanged.		'''CPY''' (Compare Y) is a 65x instruction that compares the value of the [[Y index register]] to something. Internally, this is done via a subtraction, but the difference is not stored anywhere. Thus, the purpose of CPY is to setup the flags. The index register Y is the minuend. Depending on the addressing mode used, the subtrahend will be either an immediate value or the value stored at the effective address specified by the operand. The contents at the effective address (when not using immediate data) and the Y index register both remain unchanged.

			The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	CPY assumes its operands are unsigned.		CPY assumes its operands are unsigned.

BIT

Xetheria — Wed, 06 May 2026 07:00:03 GMT

accumulator -> immediate addressing

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	'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.		'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.

	The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[~~accumulator~~ addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	Except in [[immediate addressing]], the most significant bit of the data located at the effective address (plus zero or one) is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].		Except in [[immediate addressing]], the most significant bit of the data located at the effective address (plus zero or one) is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].

CMP

Xetheria — Wed, 06 May 2026 06:59:06 GMT

accumulator -> immediate addressing

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	'''CMP''' (Compare) is a 65x instruction that compares the value of the [[accumulator]] to something. Internally, this is done via a subtraction, but the difference is discarded. Thus, the purpose of CMP is to setup the flags. The accumulator serves as the minuend and the operand serves as the subtrahend. For example, CMP #6 does "a minus 6" internally. CMP only does unsigned comparisons. In [[immediate addressing]] only, CMP is a total of 3 bytes long when the accumulator is 16 bits wide. Unlike [[SBC]], the [[carry flag]] does not affect CMP.		'''CMP''' (Compare) is a 65x instruction that compares the value of the [[accumulator]] to something. Internally, this is done via a subtraction, but the difference is discarded. Thus, the purpose of CMP is to setup the flags. The accumulator serves as the minuend and the operand serves as the subtrahend. For example, CMP #6 does "a minus 6" internally. CMP only does unsigned comparisons. In [[immediate addressing]] only, CMP is a total of 3 bytes long when the accumulator is 16 bits wide. Unlike [[SBC]], the [[carry flag]] does not affect CMP.

	The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[~~accumulator~~ addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	If the subtraction required a borrow, the carry flag is cleared (otherwise it is set).		If the subtraction required a borrow, the carry flag is cleared (otherwise it is set).

CPX

Xetheria — Wed, 06 May 2026 06:57:42 GMT

effective address plus one

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	'''CPX''' (Compare X) is a 65x instruction that compares the value of the [[X index register]] to something. Internally, this is done via a subtraction, but the difference is not stored anywhere. Thus, the purpose of CPX is to setup the flags. The index register X is the minuend. Depending on the addressing mode used, the subtrahend will be either an immediate value or the value stored at the effective address specified by the operand. The contents at the effective address (when not using immediate data) and the X index register both remain unchanged.		'''CPX''' (Compare X) is a 65x instruction that compares the value of the [[X index register]] to something. Internally, this is done via a subtraction, but the difference is not stored anywhere. Thus, the purpose of CPX is to setup the flags. The index register X is the minuend. Depending on the addressing mode used, the subtrahend will be either an immediate value or the value stored at the effective address specified by the operand. The contents at the effective address (when not using immediate data) and the X index register both remain unchanged.

			The size of the index registers determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[immediate addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	CPX assumes its operands are unsigned.		CPX assumes its operands are unsigned.

CMP

Xetheria — Wed, 06 May 2026 06:54:44 GMT

effective address plus one

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	'''CMP''' (Compare) is a 65x instruction that compares the value of the [[accumulator]] to something. Internally, this is done via a subtraction, but the difference is discarded. Thus, the purpose of CMP is to setup the flags. The accumulator serves as the minuend and the operand serves as the subtrahend. For example, CMP #6 does "a minus 6" internally. CMP only does unsigned comparisons. In [[immediate addressing]] only, CMP is a total of 3 bytes long when the accumulator is 16 bits wide. Unlike [[SBC]], the [[carry flag]] does not affect CMP.		'''CMP''' (Compare) is a 65x instruction that compares the value of the [[accumulator]] to something. Internally, this is done via a subtraction, but the difference is discarded. Thus, the purpose of CMP is to setup the flags. The accumulator serves as the minuend and the operand serves as the subtrahend. For example, CMP #6 does "a minus 6" internally. CMP only does unsigned comparisons. In [[immediate addressing]] only, CMP is a total of 3 bytes long when the accumulator is 16 bits wide. Unlike [[SBC]], the [[carry flag]] does not affect CMP.

			The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	If the subtraction required a borrow, the carry flag is cleared (otherwise it is set).		If the subtraction required a borrow, the carry flag is cleared (otherwise it is set).

BIT

Xetheria — Wed, 06 May 2026 06:52:48 GMT

effective address plus one

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	'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.		'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction. If the conjunction is zero, the [[zero flag]] is set, otherwise it is cleared.

	Except in [[immediate addressing]], the most significant bit of the data located at the effective address is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].		The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

			Except in [[immediate addressing]], the most significant bit of the data located at the effective address (plus zero or one) is moved into the [[negative flag]], and the second most significant bit of that data is moved into the [[overflow flag]]. BIT is often used right before a conditional branch instruction like [[BVC]] or [[BVS]].

	==== Syntax ====		==== Syntax ====

ASL

Xetheria — Wed, 06 May 2026 06:49:56 GMT

effective address plus one

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	'''ASL''' (Arithmetic Shift Left) is a 65x instruction that shifts every bit of a value left one bit (multiplication by two). The least significant bit is cleared. The most significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROL]]).		'''ASL''' (Arithmetic Shift Left) is a 65x instruction that shifts every bit of a value left one bit (multiplication by two). The least significant bit is cleared. The most significant bit is shifted into the [[carry flag]]. The previous value of the carry flag is lost (unlike with [[ROL]]).

	The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag.		The size of the accumulator determines how many bits are shifted (8 or 16) not including the clearing zero and carry flag. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

AND

Xetheria — Wed, 06 May 2026 06:48:52 GMT

effective address plus one

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	'''AND''' is a 65x instruction that performs a logical AND. The conjunction is stored in the [[accumulator]]. The size of the accumulator determines how much data is ANDed.		'''AND''' is a 65x instruction that performs a logical AND. The conjunction is stored in the [[accumulator]]. The size of the accumulator determines how much data is ANDed: if 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	==== Syntax ====		==== Syntax ====

ADC

Xetheria — Wed, 06 May 2026 06:46:58 GMT

effective address plus one

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	'''ADC''' (Add with Carry) is the main 65x addition instruction. The accumulator is always both one of the addends and where the sum is stored. The operand serves as the other addend.		'''ADC''' (Add with Carry) is the main 65x addition instruction. The accumulator is always both one of the addends and where the sum is stored. The operand serves as the other addend. The size of the accumulator determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low-order byte is located at the effective address and the high-order byte at the effective address plus one.

	As there is no add-without-carry instruction, a [[CLC]] should be run (or the carry flag otherwise ensured to be clear) before an ADC, or else the sum will be one greater than expected.		As there is no add-without-carry instruction, a [[CLC]] should be run (or the carry flag otherwise ensured to be clear) before an ADC, or else the sum will be one greater than expected.

65c816 Instructions

Xetheria — Mon, 04 May 2026 15:37:29 GMT

opcodes -> instructions

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	There are 92 ~~opcodes~~ in ASM. They are divided into different categories.		There are 92 instructions in ASM. They are divided into different categories.

	== Loading instructions ==		== Loading instructions ==

DEC

Xetheria — Mon, 04 May 2026 04:26:45 GMT

what happens at effective address plus one

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	'''DEC''' (Decrement) is a 65x instruction that decrements the value in the location specified by the operand by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. An alternate mnemonic when the operand is the accumulator is "DEA."		'''DEC''' (Decrement) is a 65x instruction that decrements the value in the location specified by the operand by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low byte is located at the effective address and the high byte at the effective address plus one. An alternate mnemonic when the operand is the accumulator is "DEA."

	DEC ignores the [[decimal mode flag]] and the [[carry flag]].		DEC ignores the [[decimal mode flag]] and the [[carry flag]].

INC

Xetheria — Mon, 04 May 2026 04:24:52 GMT

not using accumulator addressing

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	'''INC''' (Increment) is a 65x instruction that increments the value in the location specified by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. An alternate mnemonic when the operand is the accumulator is "INA."		'''INC''' (Increment) is a 65x instruction that increments the value in the location specified by one. The size of the [[accumulator]] determines whether this is an 8 or 16 bit operation. If 16-bit and not using [[accumulator addressing]], the low byte is located at the effective address and the high byte at the effective address plus one. An alternate mnemonic when the operand is the accumulator is "INA."

	INC ignores the [[decimal mode flag]] and the [[carry flag]].		INC ignores the [[decimal mode flag]] and the [[carry flag]].

Timing Control Unit

Xetheria — Sun, 03 May 2026 21:43:34 GMT

instructions with and without cycle penalties

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	The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.		The '''Timing Control Unit''' (TCU) is part of the [[65c816]]. It contains a counter that is reset at each instruction fetch and advances during each [[machine cycle]]. Together with the [[instruction register]], it helps the processor perform register transfers.

			==== List of instructions with cycle penalties: ====

			* [[ADC]]
			* [[AND]]
			* [[ASL]]
			* [[BCC]]
			* [[BCS]]
			* [[BEQ]]
			* [[BIT]]
			* [[BMI]]
			* [[BNE]]
			* [[BPL]]
			* [[BRA]]
			* [[BRK]]
			* [[BVC]]
			* [[BVS]]
			* [[CMP]]
			* [[COP]]
			* [[CPX]]
			* [[CPY]]
			* [[DEC]]
			* [[EOR]]
			* [[INC]]
			* [[LDA]]
			* [[LDX]]
			* [[LDY]]
			* [[LSR]]
			* [[ORA]]
			* [[PEI]]
			* [[PHA]]
			* [[PHX]]
			* [[PHY]]
			* [[PLA]]
			* [[PLX]]
			* [[PLY]]
			* [[ROL]]
			* [[ROR]]
			* [[RTI]]
			* [[SBC]]
			* [[STA]]
			* [[STX]]
			* [[STY]]
			* [[STZ]]
			* [[TRB]]
			* [[TSB]]

			==== List of instructions without cycle penalties: ====

			* [[BRL]]
			* [[CLC]]
			* [[CLD]]
			* [[CLI]]
			* [[CLV]]
			* [[DEX]]
			* [[DEY]]
			* [[INX]]
			* [[INY]]
			* [[JMP]] / JML
			* [[JSL]]
			* [[JSR]]
			* [[MVN]]
			* [[MVP]]
			* [[NOP]]
			* [[PEA]]
			* [[PER]]
			* [[PHB]]
			* [[PHD]]
			* [[PHK]]
			* [[PHP]]
			* [[PLB]]
			* [[PLD]]
			* [[PLP]]
			* [[REP]]
			* [[RTL]]
			* [[RTS]]
			* [[SEC]]
			* [[SED]]
			* [[SEI]]
			* [[SEP]]
			* [[STP]]
			* [[TAX]]
			* [[TAY]]
			* [[TCD]]
			* [[TCS]]
			* [[TDC]]
			* [[TSC]]
			* [[TSX]]
			* [[TXA]]
			* [[TXS]]
			* [[TXY]]
			* [[TYA]]
			* [[TYX]]
			* [[WAI]]
			* [[WDM]]
			* [[XBA]]
			* [[XCE]]

	=== Reference ===		=== Reference ===

blanking

Xetheria — Sun, 03 May 2026 21:17:49 GMT

created page

New page

#redirect [[Blanking]]

VRAM

Xetheria — Sun, 03 May 2026 21:17:40 GMT

only during blanking

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	VRAM is not connected to [[Address Bus A]], so the [[5A22]] must access it through I/O ports.		VRAM is not connected to [[Address Bus A]], so the [[5A22]] must access it through I/O ports.

			Devices connected to the [[cpu data bus]] can only access VRAM during vertical [[blanking]] or forced blanking.<sup>[3]</sup>

	=== See Also ===		=== See Also ===
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	=== References ===		=== References ===
	* [https://archive.org/details/SNESDevManual/book1/page/n195 Appendix A-1] of the official Super Nintendo development manual		# [https://archive.org/details/SNESDevManual/book1/page/n195 Appendix A-1] of the official Super Nintendo development manual
	* paragraph 22.4 on [https://archive.org/details/SNESDevManual/book1/page/n97 page 2-22-1 of Book I], lbid.		# paragraph 22.4 on [https://archive.org/details/SNESDevManual/book1/page/n97 page 2-22-1 of Book I], lbid.
			# fullsnes

	[[Category:SNES Hardware]]		[[Category:SNES Hardware]]

Program Bank Register

Xetheria — Fri, 01 May 2026 05:06:33 GMT

interrupts push it to the stack

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	The '''Program Bank Register''' (PBR or K) tells the [[65c816]] which [[bank]] to fetch the next opcode from. It is 8 bits wide and is cleared to zero on reset.<sup>[2]</sup> [[PHK]] ~~pushes~~ it onto the [[stack]], but there is no PLK to pull it.		The '''Program Bank Register''' (PBR or K) tells the [[65c816]] which [[bank]] to fetch the next opcode from. It is 8 bits wide and is cleared to zero on reset.<sup>[2]</sup> [[PHK]] (and most interrupts) push it onto the [[stack]], but there is no PLK to pull it.

	PBR is affected only by these intructions (and hardware [[interrupt]]s which also zero it):<sup>[4]</sup>		PBR is affected only by these intructions (and hardware [[interrupt]]s which also zero it):<sup>[4]</sup>

Processor Status Register

Xetheria — Fri, 01 May 2026 05:04:16 GMT

any interrupt pushes it to the stack

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	* 0: [[Carry Flag]] - C		* 0: [[Carry Flag]] - C

	It can be pulled from the [[stack]] via [[PLP]] and [[RTI]]. To push it to the stack, use [[PHP]]. [[COP]] and [[BRK]] also push it to the stack.		It can be pulled from the [[stack]] via [[PLP]] and [[RTI]]. To push it to the stack, use [[PHP]]. [[COP]] and [[BRK]] (indeed most interrupts) also push it to the stack.

	There are nine instructions that directly modify these flags, including:<sup>[3]</sup>		There are nine instructions that directly modify these flags, including:<sup>[3]</sup>

Program Counter

Xetheria — Fri, 01 May 2026 05:01:20 GMT

interrupts

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	The 6502 had 16-bit absolute addressing but only an 8-bit adder, so in [[emulation mode]] branches that cross a page boundary incur a one cycle penalty. 65c816 native mode has no such penalty because the full 16-bit adder is used.		The 6502 had 16-bit absolute addressing but only an 8-bit adder, so in [[emulation mode]] branches that cross a page boundary incur a one cycle penalty. 65c816 native mode has no such penalty because the full 16-bit adder is used.

			Interrupts cause the program counter to be pushed to the stack (high byte first).

	=== See Also ===		=== See Also ===

Interrupt Handler

Xetheria — Fri, 01 May 2026 01:20:18 GMT

RESB

Xetheria — Thu, 30 Apr 2026 23:47:16 GMT

created page

New page

#redirect [[Reset Traces]]

Interrupt Logic

Xetheria — Thu, 30 Apr 2026 23:47:00 GMT

added RESB

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	The '''Interrupt Logic''' circuit exists on the [[65c816]]. ~~Three~~ types of interrupts are supported on a stock 65c816:		The '''Interrupt Logic''' circuit exists on the [[65c816]]. Four types of interrupts are supported on a stock 65c816:

	* [[NMI]]		* [[NMI]]
	* [[IRQ]]		* [[IRQ]]
	* [[ABORT]] (not supported on the SNES)<sup>[2]</sup>		* [[ABORT]] (not supported on the SNES)<sup>[2]</sup>
			* [[RESB]] (not counted by [[Labiak]] textbook)

	=== References ===		=== References ===

Zero Page Addressing

Xetheria — Thu, 30 Apr 2026 22:33:08 GMT

Transfer Switches

Xetheria — Thu, 30 Apr 2026 16:49:59 GMT

all 16 bits output

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	* Internal Special Bus		* Internal Special Bus
	* Internal Data Bus		* Internal Data Bus

			All register transfers output 16 bits from the source register, but not all 16 bits are always stored.

	=== References ===		=== References ===
	* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/n604 page 578]		* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/n604 page 578]
	* Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram on page 8 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf		* Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram on page 8 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
			* section 7.20 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers of 65c816 datasheet

	[[Category:SNES Hardware]]		[[Category:SNES Hardware]]

Interrupt Request

Xetheria — Thu, 30 Apr 2026 16:43:14 GMT

External Links: which section of 65c816 datasheet

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	=== External Links ===		=== External Links ===
	# snes9x implementation of IRQ: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2588		# snes9x implementation of IRQ: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2588
	# 65c816 datasheet		# section 7.19 Interrupt Priorities of 65c816 datasheet
	# https://problemkaputt.de/fullsnes.htm#snesppuinterrupts		# https://problemkaputt.de/fullsnes.htm#snesppuinterrupts

	[[Category:ASM]]		[[Category:ASM]]
	[[Category:Official Jargon]]		[[Category:Official Jargon]]

Instruction Register

Xetheria — Thu, 30 Apr 2026 14:56:43 GMT

Inherited from 6502 category

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	[[Category:SNES Hardware]]		[[Category:SNES Hardware]]
	[[Category:Registers]]		[[Category:Registers]]
			[[Category:Inherited from 6502]]

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	Use [[BRK]] to force a software interrupt.		Use [[BRK]] to force a software interrupt.

			When an interrupt occurs, the [[program bank register]], [[program counter]] (high then low), and [[status register]] are pushed to the [[stack]] (in this order).

	Return control back with [[RTI]] when on the [[65c816]] or [[RETI]] when on the [[SPC700]].		Return control back with [[RTI]] when on the [[65c816]] or [[RETI]] when on the [[SPC700]].
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	* [[IRQ]]		* [[IRQ]]
	* [[WAI]]		* [[WAI]]
			* [[Interrupt Request]]

	[[Category:ASM]]		[[Category:ASM]]

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	* [[Implied Addressing]]		* [[Implied Addressing]]
	* [[Absolute Addressing]]		* [[Absolute Addressing]]

			=== Reference ===
			* section 4.11 Zero Page zp of 65c02 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf

	[[Category:ASM]]		[[Category:ASM]]
	[[Category:Addressing Modes]]		[[Category:Addressing Modes]]
	[[Category:Inherited from 6502]]		[[Category:Inherited from 6502]]