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Instruction Register: Difference between revisions
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The '''Instruction Register''' exists on the [[65c816]]. It is 8 bits wide. | The '''Instruction Register''' (IR) exists on the [[65c816]]. It is 8 bits wide and contains the opcode just fetched from memory. It is not accessible to the programmer. | ||
It is connected to the data latch/predecoder and instruction decode minterms. | |||
=== References === | === References === | ||
* https://archive.org/details/Programming_the_65816/page/n49 | * [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n49 page 39] | ||
* section 2.1 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | * section 2.1 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Registers]] | |||
Latest revision as of 20:16, 9 August 2024
The Instruction Register (IR) exists on the 65c816. It is 8 bits wide and contains the opcode just fetched from memory. It is not accessible to the programmer.
It is connected to the data latch/predecoder and instruction decode minterms.
References
- Labiak, page 39
- section 2.1 on page 6 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf