SBK (Super FX): Difference between revisions

Latest revision as of 05:18, 16 July 2024


Basic Info
Addressing Mode	Opcode	Length	ROM Speed	RAM Speed	Cache Speed
Implied (type 1)	90	1 byte	3 to 8 cycles	7 to 11 cycles	1 to 6 cycles


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.	.	.	.

SBK is a Super FX instruction that uses bulk processing. It stores the value in the source register to the address in the ram address cache.

The ALT0 state is restored.

The source register should be specified in advance using WITH or FROM. Otherwise, R₀ serves as the default.

SBK

Let:

(70:3230h) = 51h
(70:3231h) = 49h
RAMBR = 70h

After executing this program:

LM   R₁, (3230h)
INC  R₁
SBK

We have:

R₁ = 4952h
(70:3230h) = 52h
(70:3231h) = 49h

Official Super Nintendo development manual on SBK: 9.79 on page 2-9-109 of Book II

@@ Line 9: / Line 9: @@
 |'''Cache Speed'''
 |+
-|
+|[[Implied]] (type 1)
 |90
 |1 byte
@@ Line 26: / Line 26: @@
 |[[Sign Flag|S]]
 |[[CY]]
-|Z
+|[[Zero Flag|Z]]
 |+
 |0
@@ Line 37: / Line 37: @@
 |}
-'''SBK''' is a [[Super FX]] instruction that uses [[Bulk Processing]]. It stores the value in the [[source register]] to the address in the [[Ram Address Cache (Super FX)|ram address cache]].
+'''SBK''' is a [[Super FX]] instruction that uses [[bulk processing]]. It stores the value in the [[source register]] to the address in the [[Ram Address Cache (Super FX)|ram address cache]].
+The [[ALT0]] state is restored.
+The source register should be specified in advance using [[WITH]] or [[FROM]].  Otherwise, R<sub>0</sub> serves as the default.
+==== Syntax ====
+<pre>
+SBK
+</pre>
+==== Example ====
+Let:
+ (70:3230h) = 51h
+ (70:3231h) = 49h
+ RAMBR = 70h
+After executing this program:
+ LM   R<sub>1</sub>, (3230h)
+ INC  R<sub>1</sub>
+ SBK
+We have:
+ R<sub>1</sub> = 4952h
+ (70:3230h) = 52h
+ (70:3231h) = 49h
 === External Links ===
@@ Line 46: / Line 69: @@
 [[Category:Data Transfer Instructions]]
 [[Category:One-byte Instructions]]
+[[Category:Expects Sreg/Dreg Prearranged]]