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SA-1

From SnesLab
Revision as of 13:05, 19 May 2019 by Vitor Vilela (talk | contribs) (Table of Contents with limited depth to not show all registers)
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Nintendo SA-1 is an enhancement chip made by Nintendo, used in 33 SNES games. The RF5A123 chip is based on the 65c816 processor, the same one used by the main SNES CPU, the RF5A22. With identical architectures to the SNES one, the chip is ideal for games and ROM hacks that would like to use the code from the main CPU, thus not having to learn an additional assembling language.

Features

With the 10.74 MHz base clock speed, which is four times faster compared to the 2.68 MHz base speed from the S-CPU. In addition to that, it includes with additional hardware circuits for data I/O, bitmap manipulation modes and additional arithmetic registers.

  • 16-bit 65c816 processor clocked at 10.74 MHz.
  • 2 kB fast internal work memory (I-RAM), clocked at 10.74 MHz.
  • Multi-processor processing, with parallel operating mode and memory sharing control.
  • Large capacity memory, with a total capability of 8 MB of ROM and 256 kB of BW-RAM, both clocked at 5.37 MHz, with ROM having an effective 10.74 MHz speed due of its 16-bit data bus.
  • High speed arithmetic hardware of multiplication, division and cumulative sum (multiply with add).
  • Bitmap and Character Conversion functions for fast graphics manipulation.
  • Custom DMA circuit for fast transfers between ROM, I-RAM and BW-RAM.
  • Variable-Length Bit data processing for enhanced algorithms such as graphics and data compression.
  • Super MMC memory mapping capabilities for BW-RAM and bank switching for multiple ROM image access and mirroring.

ROM Hacking

SA-1 Root and SA-1 Pack are known patches used for enabling SA-1 on SNES games that didn't include the chip previously and had problems with slowdown, such as Super Mario World and Gradius III.

Technical Information

Hardware Registers

Register Summary

Write Registers

Address Length Code Access Description
$2200 1 byte CCNT SNES SA-1 CPU CONTROL
$2201 1 byte SIE SNES SUPER NES CPU INT ENABLE
$2202 1 byte SIC SNES SUPER NES CPU INT CLEAR
$2203 2 bytes CRV SNES SA-1 CPU RESET VECTOR
$2205 2 bytes CNV SNES SA-1 CPU NMI VECTOR
$2207 2 bytes CIV SNES SA-1 CPU IRQ VECTOR
$2209 1 byte SCNT SA-1 SUPER NES CPU CONTROL
$220A 1 byte CIE SA-1 SA-1 CPU INT ENABLE
$220B 1 byte CIC SA-1 SA-1 CPU INT CLEAR
$220C 2 bytes SNV SA-1 SUPER NES CPU NMI VECTOR
$220E 2 bytes SIV SA-1 SUPER NES CPU IRQ VECTOR
$2210 1 byte TMC SA-1 H/V TIMER CONTROL
$2211 1 byte CTR SA-1 SA-1 CPU TIMER RESTART
$2212 2 bytes HCNT SA-1 SET H-COUNT
$2214 2 bytes VCNT SA-1 SET V-COUNT
$2220 1 byte CXB SNES SET SUPER MMC BANK C
$2221 1 byte DXB SNES SET SUPER MMC BANK D
$2222 1 byte EXB SNES SET SUPER MMC BANK E
$2223 1 byte FXB SNES SET SUPER MMC BANK F
$2224 1 byte BMAPS SNES SUPER NES CPU BW-RAM ADDRESS MAPPING
$2225 1 byte BMAP SA-1 SA-1 CPU BW-RAM ADDRESS MAPPING
$2226 1 byte SBWE SNES SUPER NES CPU BW-RAM WRITE ENABLE
$2227 1 byte CBWE SA-1 SA-1 CPU BW-RAM WRITE ENABLE
$2228 1 byte BPWA SNES BW-RAM WRITE-PROTECTED AREA
$2229 1 byte SIWP SNES SA-1 I-RAM WRITE PROTECTION
$222A 1 byte CIWP SA-1 SA-1 I-RAM WRITE PROTECTION
$2230 1 byte DCNT SA-1 DMA CONTROL
$2231 1 byte CDMA Both CHARACTER CONVERSION OMA PARAMETERS
$2232 3 bytes SDA Both DMA SOURCE DEVICE START ADDRESS
$2235 3 bytes DDA Both DMA DESTINATION START ADDRESS
$2238 2 bytes DTC SA-1 DMA TERMINAL COUNTER
$223F 1 byte BBF SA-1 BW-RAM BIT MAP FORMAT
$2240 16 bytes BRF SA-1 BIT MAP REGISTER FILE
$2250 1 byte MCNT SA-1 ARITHMETIC CONTROL
$2251 2 bytes MA SA-1 ARITHMETIC PARAMETERS: MULTIPLICAND/DIVIDEND
$2253 2 bytes MB SA-1 ARITHMETIC PARAMETERS: MULTIPLIER/DIVISOR
$2258 1 byte VBD SA-1 VARIABLE-LENGTH BIT PROCESSING
$2259 3 bytes VDA SA-1 VARIABLE-LENGTH BIT GAME PAK ROM START ADDRESS

Read Registers

Address Length Code Access Description
$2300 1 bytes SFR SNES SUPER NES CPU FLAG READ
$2301 1 bytes CFR SA-1 SA-1 CPU FLAG READ
$2302 2 bytes HCR SA-1 H-COUNT READ
$2304 2 bytes VCR SA-1 V-COUNT READ
$2306 5 bytes MR SA-1 ARITHMETIC RESULT [PRODUCT/QUOTIENT/ACCUMULATIVE SUM]
$230B 1 bytes OF SA-1 ARITHMETIC OVERFLOW FLAG
$230C 2 bytes VDP SA-1 VARIABLE-LENGTH DATA READ PORT
$230E 1 byte VC SNES VERSION CODE REGISTER (OPEN BUS)

Register Details

$2200 - SA-1 CPU CONTROL

$2201 - SUPER NES CPU INT ENABLE

$2202 - SUPER NES CPU INT CLEAR

$2203 - SA-1 CPU RESET VECTOR

$2205 - SA-1 CPU NMI VECTOR

$2207 - SA-1 CPU IRQ VECTOR

$2209 - SUPER NES CPU CONTROL

$220A - SA-1 CPU INT ENABLE

$220B - SA-1 CPU INT CLEAR

$220C - SUPER NES CPU NMI VECTOR

$220E - SUPER NES CPU IRQ VECTOR

$2210 - H/V TIMER CONTROL

$2211 - SA-1 CPU TIMER RESTART

$2212 - SET H-COUNT

$2214 - SET V-COUNT

$2220 - SET SUPER MMC BANK C

$2221 - SET SUPER MMC BANK D

$2222 - SET SUPER MMC BANK E

$2223 - SET SUPER MMC BANK F

$2224 - SUPER NES CPU BW-RAM ADDRESS MAPPING

$2225 - SA-1 CPU BW-RAM ADDRESS MAPPING

$2226 - SUPER NES CPU BW-RAM WRITE ENABLE

$2227 - SA-1 CPU BW-RAM WRITE ENABLE

$2228 - BW-RAM WRITE-PROTECTED AREA

$2229 - SA-1 I-RAM WRITE PROTECTION

$222A - SA-1 I-RAM WRITE PROTECTION

$2230 - DMA CONTROL

$2231 - CHARACTER CONVERSION OMA PARAMETERS

$2232 - DMA SOURCE DEVICE START ADDRESS

$2235 - DMA DESTINATION START ADDRESS

$2238 - DMA TERMINAL COUNTER

$223F - BW-RAM BIT MAP FORMAT

$2240 - BIT MAP REGISTER FILE

$2250 - ARITHMETIC CONTROL

$2251 - ARITHMETIC PARAMETERS: MULTIPLICAND/DIVIDEND

$2253 - ARITHMETIC PARAMETERS: MULTIPLIER/DIVISOR

$2258 - VARIABLE-LENGTH BIT PROCESSING

$2259 - VARIABLE-LENGTH BIT GAME PAK ROM START ADDRESS

$2300 - SUPER NES CPU FLAG READ

$2301 - SA-1 CPU FLAG READ

$2302 - H-COUNT READ

$2304 - V-COUNT READ

$2306 - ARITHMETIC RESULT [PRODUCT/QUOTIENT/ACCUMULATIVE SUM]

$230B - ARITHMETIC OVERFLOW FLAG

$230C - VARIABLE-LENGTH DATA READ PORT

$230E - VERSION CODE REGISTER (OPEN BUS)

Memory and Bus

Memory Map

SNES Side

SA-1 Side

Open Bus Behavior

ROM

I-RAM

Write Protection

BW-RAM

Write Protection

Virtual Bitmap Memory

Super MMC

Bus Conflicts

Direct Memory Access

Character Conversion DMA

Parallel DMA

Interactions with SNES DMA

Undefined Behavior

Variable Length Bit

Fixed Mode

Automatic Mode

Mixed Mode

Arithmetic Operations

Multiplication

Division

Cumulative Sum

Parallelism and I/O

IRQ

NMI

FastROM Interactions