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Super FX

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Revision as of 23:24, 16 October 2021 by MarioFanGamer (talk | contribs) (Added information to memory mapping. TODO: Fix table.)
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Super FX is a Super NES enhancement chip developed by Argonaut Games and Nintendo. It's also known as the "Graphical Support Unit" (short for "GSU") for its greater graphical capabilities compared to the S-CPU whereas its first revision, used for Star Fox, uses the name "Mathematical, Argonaut, Rotation, & Input/Output" or short MARIO chip. It also is know for the use in Super Mario World 2: Yoshi's Island.

During this article, GSU refers to Super FX whereas CPU refers to the Super NES CPU.

Features

The embedded co-processor has got a base clock speed of 10.74 MHz which is four times as fast as the S-CPU which uses a base block of 2.68 Mhz. Its features includes but not limited to:

  • A RISC-like processor where most opcodes have an instruction size of one byte and are executed in a single cycle when in cache.
  • 512 bytes of cache RAM for faster processing of instructions.
  • A large memory capactiy, a total capacity of 8 MiB ROM, of which two MiB are shared by CPU and GSU, and 256 KiB RAM, of which 128 KiB are shared by CPU and GSU.
  • A separate bus for ROM and RAM to handle memory in parallel
  • Paralell processing with the CPU
  • Fast Bitmap to Planar conversion
  • Pipeline processing to fetch opcodes twice as fast, effectively increasing the processing speed to 21.48 MHz.

Technical Information

Hardware Registers

Memory and Bus

Memory Map

One advantage of Super FX is that it naturally supports ROMs with a size of up to 8 MiB. However, Super FX can only use the first two MiB of a ROM. Similarly, even though a single cartridge may have up to 256 KiB of SRAM, only half of them can be used by SRAM. As a result, there is a difference between the CPU and GSU mapping.

This is how the ROM is mapped from the perspective of the CPU:

Banks Address Description
$00-$3F $0000-$1FFF WRAM mirror
$2100-$21FF PPU registers
$3000-$3FFF Super FX registers
$4200-$43FF CPU registers
$6000-$7FFF SRAM mirror
$8000-$FFFF ROM (LoROM)
$40-$5F $0000-$FFFF ROM (HiROM)
$60-$6F $0000-$FFFF Unmapped
$70-$71 $0000-$FFFF SRAM
$7C-$7D $0000-$FFFF Backup RAM
$7E-$7F $0000-$FFFF WRAM
$80-$BF $0000-$1FFF WRAM mirror
$2100-$21FF PPU registers
$3000-$3FFF Super FX registers
$4200-$43FF CPU registers
$6000-$7FFF SRAM mirror
$8000-$FFFF ROM (LoROM)
$C0-$FF $8000-$FFFF ROM (HiROM)

The GSU memory map looks similar to the CPU mapping but only with access to ROM and SRAM as well as only access to 2 MiB of ROM and 128 KiB of SRAM. As a result, it looks more like this:

Banks Address Description
$00-$3F $0000-$7FFF Unmapped
$8000-$FFFF ROM (LoROM)
$40-$5F $0000-$FFFF ROM (HiROM)
$60-$6F $0000-$FFFF Unmapped
$70-$71 $0000-$FFFF SRAM
$72-$7F $0000-$FFFF Unmapped
$80-$FF $0000-$FFFF Mirror of $00-$7F

Finally, it should be noted that banks $40-$5F are HiROM mirrors of the LoROM banks $00-$3F interlaced so addresses such as $008000 and $400000 are identical.

ROM

RAM

Pipeline Processing

Cache

Bus Conflicts

Bitmap Processing