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Super FX: Difference between revisions
From SnesLab
(I have rewritten the whole page. The information comes from SMWiki, back when the knowledge of Super FX wasn't as large as it is now. It contained some misinformation as well (despite ironically clarifying them). Instruction will probably be put at another page. And yes, it is based of the current SA-1 page.) |
m (Misspelt Argonaut Games as "Argonauts Games".) |
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'''Super FX''' is a [[Super NES]] [[enhancement chip]] developed by [https://en.wikipedia.org/wiki/Argonaut_Games | '''Super FX''' is a [[Super NES]] [[enhancement chip]] developed by [https://en.wikipedia.org/wiki/Argonaut_Games Argonaut Games] and [http://en.wikipedia.org/wiki/Nintendo Nintendo]. It's also known as the "Graphical Support Unit" (short for "GSU") for its greater graphical capabilities compared to the S-CPU whereas its first revision, used for [[Star Fox]], uses the name "Mathematical, Argonaut, Rotation, & Input/Output" or short MARIO chip. It also is know for the use in [[Super Mario World 2: Yoshi's Island]]. | ||
During this article, GSU refers to Super FX whereas CPU refers to the Super NES CPU. | During this article, GSU refers to Super FX whereas CPU refers to the Super NES CPU. | ||
Revision as of 09:21, 9 October 2021
Super FX is a Super NES enhancement chip developed by Argonaut Games and Nintendo. It's also known as the "Graphical Support Unit" (short for "GSU") for its greater graphical capabilities compared to the S-CPU whereas its first revision, used for Star Fox, uses the name "Mathematical, Argonaut, Rotation, & Input/Output" or short MARIO chip. It also is know for the use in Super Mario World 2: Yoshi's Island.
During this article, GSU refers to Super FX whereas CPU refers to the Super NES CPU.
Features
The embedded co-processor has got a base clock speed of 10.74 MHz which is four times as fast as the S-CPU which uses a base block of 2.68 Mhz. Its features includes but not limited to:
- A RISC-like processor where most opcodes have an instruction size of one byte and are executed in a single cycle when in cache.
- 512 bytes of cache RAM for faster processing of instructions.
- A large memory capactiy, a total capacity of 8 MiB ROM, of which two MiB are shared by CPU and GSU, and 256 KiB RAM, of which 128 KiB are shared by CPU and GSU.
- A separate bus for ROM and RAM to handle memory in parallel
- Paralell processing with the CPU
- Fast Bitmap to Planar conversion
- Pipeline processing to fetch opcodes twice as fast, effectively increasing the processing speed to 21.48 MHz.