SA-1 Hardware Behavior: Difference between revisions

Revision as of 20:08, 21 July 2019

Registers

Memory Map

BW-RAM

Mapped on banks $40-$4F on SNES CPU side (up to 1 MiB).
Mapped on banks $40-$5F on SA-1 CPU side (up to 2 MiB).
SA-1 has enough pins for mapping up to 256 KB of BW-RAM. Assign #$08 to $00:FFD8.

Virtual Memory

Virtual memory is only present on SA-1 CPU memory map.
It's mapped on banks $60-$7F.
Allows reading only two or four bits of the BW-RAM, useful for storing packed 4bpp or 2bpp pixels.

Variable Length Bit Processing

Only works with even address. The least significant bit is completely ignored.
- That means ROM addresses like $00:8001 will be read as $00:8000 instead.
The address expects the actual SA-1 ROM memory map.
- However, regions that does not map to ROM will just mirror to the bank 0 instead.
  - For example, $00:0000-$00:7FFF is the same as $00:8000-$00:FFFF.
- For banks $40-$7F, *everything* is bank 0 mirror (LoROM!)
  - $41:8000 will actually mirror to $00:8000 (LoROM) and NOT $01:8000 like expected.
Banks $C0-$FF works as expected (HiROM).

Overall, divide the memory map in 32 KB blocks:

$00-$3F; $80-$BF: LoROM memory (starting at $8000)
$C0-$FF: HiROM memory map
Everything else: Mirror to bank 0.

Why are the odd addresses completely ignored? This is simple to explain: because the SA-1 ROM has a 16-bit bus, so the address is halved when tossed to the ROM circuit, discarding the low byte. It does not add any special treatment for reading the high byte first or something.

Variable Length Bit reading automatic mode DOES NOT WORK on my cart. It always automatically shifts 16-bit words regardless of the setting you select, when picking auto mode. This may need more studies. Fixed mode works fine.

FastROM

You can enable FastROM on a SA-1 ROM.

However when enabling it, the SA-1 chip is paused whenever SNES attempts a fast ROM reading, but it won't crash. Its controller is smart enough to allocate all of its I/O resources and hand to the S-CPU.

The behavior is only present on the actual FastROM accesses. Accessing though DMA or banks $00-$7F, the SA-1 CPU speed is not affected and it will treat as SlowROM reads.

This is extremely clever and even more if you consider that's only possible with the chip monitoring changes to the $420D register.

Usage

Is there any point in using FastROM on a SA-1 ROM if the chip will end up getting paused? Yes!

You can always trigger an IRQ when calling SA-1 on WRAM. That means if you only use SA-1 only or S-CPU only per time, you can get the best speed of both with 10.73 and 3.58 MHz, with one paused while the other one is running.

However, there is no trace of games using this behavior.

@@ Line 1: / Line 1: @@
-) Banks $50-$5F and $70-$7F are mapped on SA-1 CPU side.
+== Registers ==
-$50-$5F is BW-RAM mirror. That means everything between banks $40 and $5F is BW-RAM. Does that mean SA-1 could map up to 2 *MEGABYTES* of RAM?
+== Memory Map ==
-There is no such answer for that. There are only enough pins for 256 *KILOBYTES* of RAM.
+=== BW-RAM ===
+* Mapped on banks $40-$4F on SNES CPU side (up to 1 MiB).
+* Mapped on banks $40-$5F on SA-1 CPU side (up to 2 MiB).
+* SA-1 has enough pins for mapping up to 256 KB of BW-RAM. Assign #$08 to $00:FFD8.
-There is no info about how to activate 256KB of BW-RAM, but please make $00:FFD8 = #$08 give 256 KB for SA-1 and not 0 KB currently.
+=== Virtual Memory ===
+* Virtual memory is only present on SA-1 CPU memory map.
+* It's mapped on banks $60-$7F.
+* Allows reading only two or four bits of the BW-RAM, useful for storing packed 4bpp or 2bpp pixels.
-Only banks $40-$4F and $60-$6F are mapped on SNES side.
+== Variable Length Bit Processing ==
+* Only works with even address. The least significant bit is completely ignored.
+** That means ROM addresses like $00:8001 will be read as $00:8000 instead.
+* The address expects the actual SA-1 ROM memory map.
+** However, regions that does not map to ROM will just mirror to the bank 0 instead.
+*** For example, $00:0000-$00:7FFF is the same as $00:8000-$00:FFFF.
+** For banks $40-$7F, *everything* is bank 0 mirror (LoROM!)
+*** $41:8000 will actually mirror to $00:8000 (LoROM) and NOT $01:8000 like expected.
+* Banks $C0-$FF works as expected (HiROM).
-$70-$7F is the virtual memory mapping as well (so it continues the data though $60-$6F).
+Overall, divide the memory map in 32 KB blocks:
+* $00-$3F; $80-$BF: LoROM memory (starting at $8000)
-Virtual memory allows reading only two or four bits of the BW-RAM, useful for storing packed 4bpp or 2bpp pixels.
+* $C0-$FF: HiROM memory map
+* Everything else: Mirror to bank 0.
-You can also **read** the virtual memory region just fine. The official SNES doc only stated about **writing** to said region.
-**SA-1 VARIABLE LENGTH BIT PROCESSING**
-The circuit responsible for the SA-1 bit stream feature has a few oddities.
-) It only accepts even addresses. The least significant bit is completely ignored.
-That means ROM addresses like $00:8001 will be read as $00:8000 instead.
-) The address expects the actual memory map.
-However regions that does not map to ROM will just mirror to bank 0 instead
-For example, $00:0000-$00:7FFF is the same as $00:8000-$00:FFFF.
-Even worse, for banks $40-$7F, *everything* is bank 0 mirror (LoROM!)
-$41:8000 will actually mirror to $00:8000 (LoROM) and NOT $01:8000 like expected.
-Banks $C0-$FF works as expected (HiROM).
-In other words, divide the memory map in 32 KB blocks.
-$00-$3F; $80-$BF: LoROM ($8000)
-$C0-$FF: HiROM
-Everything else: Mirror to bank 0.
-Everything else includes banks $00-$3F; $80-$BF 32KB blocks of $0000-$7FFF and all 32KB blocks of banks $40-$7F.
 Why are the odd addresses completely ignored? This is simple to explain: because the SA-1 ROM has a 16-bit bus, so the address is halved when tossed to the ROM circuit, discarding the low byte. It does not add any special treatment for reading the high byte first or something.
@@ Line 46: / Line 32: @@
 Variable Length Bit reading automatic mode DOES NOT WORK on my cart. It always automatically shifts 16-bit words regardless of the setting you select, when picking auto mode. This may need more studies. Fixed mode works fine.
-**IMPORTANT**
+== FastROM ==
 You can enable FastROM on a SA-1 ROM.
-What happens? The SA-1 chip is paused whenever SNES attempts a fast ROM reading, however it does not crash. The system is smart enough to allocate all of its I/O resources and hand to the SNES system.
+However when enabling it, the SA-1 chip is paused whenever SNES attempts a fast ROM reading, but it won't crash. Its controller is smart enough to allocate all of its I/O resources and hand to the S-CPU.
-However, that behavior only exists on the actual FastROM accesses. Accessing though DMA or banks $00-$7F, the SA-1 CPU speed is not affected.
+The behavior is only present on the actual FastROM accesses. Accessing though DMA or banks $00-$7F, the SA-1 CPU speed is not affected and it will treat as SlowROM reads.
 This is extremely clever and even more if you consider that's only possible with the chip monitoring changes to the $420D register.
-I have accidentally made HDMA access not use FastROM access and I ran out of erased ROM chips. But I need to make sure the speed is not affected by HDMA as well to confirm this. DMA reads from bank $C0 which is FastROM.
+=== Usage ===
+Is there any point in using FastROM on a SA-1 ROM if the chip will end up getting paused? Yes!
-But is there any point in using FastROM on a SA-1 ROM if the chip will end up getting paused? Yes!
+You can always trigger an IRQ when calling SA-1 on WRAM. That means if you only use SA-1 only or S-CPU only per time, you can get the best speed of both with 10.73 and 3.58 MHz, with one paused while the other one is running.
-You can always trigger an IRQ when calling SA-1 on WRAM. That means if you only use SA-1 only or S-CPU only per time, you can get the best speed of both with 10.73 and 3.58 MHz, with one paused while the other one is running.
+However, there is no trace of games using this behavior.