SA-1 Hardware Behavior

Registers

• $2200-$22FF are write-only registers.
• $2300-$23FF are read-only registers.
• SNES can only read $2300. The rest is open-bus.

Memory Map

ROM

• Speed: 5.37 MHz on SA-1 and 3.58 MHz on SNES.
• However because the ROM has a 16-bit data bus, the effective speed is 10.74 MHz on SA-1 CPU.
  • The chip will always make word reads from it when SNES CPU accesses it. Thus, effectively making the SA-1 chip access the ROM at 2.68 MHz (but with 5.37 MHz effective speed).
• Cycle penalty: because of the 16-bit databus, the SA-1 will get one or more 10.74 MHz cycle penalties when:
  • Jumps or reads an odd address.
  • Only read a single byte from the ROM.
  • Branch and end up not using the higher 16-bit word.
• Overall, cycle penalties happen when it's not possible to take full advantage of the 16-bit data bus of the ROM and when it has the multiplex accesses together the SNES CPU.

I-RAM

• Speed: 10.74 MHz on SA-1 and 3.58 MHz on SNES.
• Cycle penalty is not well-explained so far.
• Maximum size is 2 kB.
• Mapped on banks $00-$3F and $80-$BF.
• Accessible on addresses $3000-$37FF on SNES CPU memory map.
• Accessible on addresses $3000-$37FF and $0000-$07FF on SA-1 CPU memory map.

BW-RAM

• Speed: 5.37 MHz on SA-1 and 2.68 MHz on SNES.
• Two-phrase access: When SNES attempts reading or writing to it, SA-1 must wait before accessing it. Effective speed is 2.68 MHz on worst case for SA-1 CPU.
• Mapped on banks $40-$4F on SNES CPU side (up to 1 MiB).
• Mapped on banks $40-$5F on SA-1 CPU side (up to 2 MiB).
• SA-1 has enough pins for mapping up to 256 KB of BW-RAM. Assign #$08 to $00:FFD8.

Virtual Memory

• Virtual memory is only present on SA-1 CPU memory map.
• It's mapped on banks $60-$7F.
• Allows reading only two or four bits of the BW-RAM, useful for storing packed 4bpp or 2bpp pixels.

Variable Length Bit Processing

• Only works with even address. The least significant bit is completely ignored.
  • That means ROM addresses like $00:8001 will be read as $00:8000 instead.
• The address expects the actual SA-1 ROM memory map.
  • However, regions that does not map to ROM will just mirror to the bank 0 instead.
    • For example, $00:0000-$00:7FFF is the same as $00:8000-$00:FFFF.
  • For banks $40-$7F, *everything* is bank 0 mirror (LoROM!)
    • $41:8000 will actually mirror to $00:8000 (LoROM) and NOT $01:8000 like expected.
• Banks $C0-$FF works as expected (HiROM).

Overall, divide the memory map in 32 KB blocks:

• $00-$3F; $80-$BF: LoROM memory (starting at $8000)
• $C0-$FF: HiROM memory map
• Everything else: Mirror to bank 0.

Why are the odd addresses completely ignored? This is simple to explain: because the SA-1 ROM has a 16-bit bus, so the address is halved when tossed to the ROM circuit, discarding the low byte. It does not add any special treatment for reading the high byte first or something.

Variable Length Bit reading automatic mode DOES NOT WORK on my cart. It always automatically shifts 16-bit words regardless of the setting you select, when picking auto mode. This may need more studies. Fixed mode works fine.

FastROM

You can enable FastROM on a SA-1 ROM.

However when enabling it, the SA-1 chip is paused whenever SNES attempts a fast ROM reading, but it won't crash. Its controller is smart enough to allocate all of its I/O resources and hand to the S-CPU.

The behavior is only present on the actual FastROM accesses. Accessing though DMA or banks $00-$7F, the SA-1 CPU speed is not affected and it will treat as SlowROM reads.

This is extremely clever and even more if you consider that's only possible with the chip monitoring changes to the $420D register.

Usage

Is there any point in using FastROM on a SA-1 ROM if the chip will end up getting paused? Yes!

You can always trigger an IRQ when calling SA-1 on WRAM. That means if you only use SA-1 only or S-CPU only per time, you can get the best speed of both with 10.73 and 3.58 MHz, with one paused while the other one is running.

However, there is no trace of games using this behavior.