AND

Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	29	2 bytes	2 cycles*
Absolute	2D	3 bytes	4 cycles*
Absolute Long	2F	4 bytes	5 cycles*
Direct Page	25	2 bytes	3 cycles*
Direct Page Indirect	32	2 bytes	5 cycles*
Direct Page Indirect Long	27	2 bytes	6 cycles*
absolute indexed by X	3D	3 bytes	4 cycles*
absolute long indexed by X	3F	4 bytes	5 cycles*
absolute indexed by Y	39	3 bytes	4 cycles*
direct page indexed by X	35	2 bytes	4 cycles*
direct page indirect indexed by X	21	2 bytes	6 cycles*
direct page indirect indexed by Y	31	2 bytes	5 cycles*
direct page indirect long indexed by Y	37	2 bytes	6 cycles*
Stack Relative	23	2 bytes	4 cycles*
stack relative indirect indexed by Y	33	2 bytes	7 cycles*

Flags Affected
N	V	M	X	D	I	Z	C
	.	.	.	.	.		.

AND is a 65x instruction that performs a logical AND. The conjunction is stored in the accumulator.

Cycle Penalties

• In all addressing modes, AND takes one extra cycle when the accumulator is 16 bits wide.
• In direct page addressing modes only, AND takes an extra cycle if the low byte of the direct page register is nonzero.
• In both Absolute Indexed addressing modes and DP Indirect Indexed by Y admodes, AND takes an extra cycle if adding the index crosses a page boundary.

See Also

• ORA
• EOR
• BIT

External Links

• Eyes & Lichty page 425 on AND: https://archive.org/details/0893037893ProgrammingThe65816/page/n451
• Labiak page 116 on AND: https://archive.org/details/Programming_the_65816/page/n125
• MCS6500 Manual page on AND: https://archive.org/details/mos_microcomputers_programming_manual/page/n35
• Carr page on AND: https://archive.org/details/6502UsersManual/page/n259
• Leventhal page 3-40 on AND: https://archive.org/details/6502-assembly-language-programming/page/n89
• undisbeliever on AND: https://undisbeliever.net/snesdev/65816-opcodes.html#and-and-accumulator-with-memory