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CLC: Difference between revisions

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* [[Eyes & Lichty]] page 441, on CLC: https://archive.org/details/0893037893ProgrammingThe65816/page/n467
* [[Eyes & Lichty]] page 441, on CLC: https://archive.org/details/0893037893ProgrammingThe65816/page/n467
* [[Labiak]] page 130 on CLC: https://archive.org/details/Programming_the_65816/page/n140
* [[Labiak]] page 130 on CLC: https://archive.org/details/Programming_the_65816/page/n140
* [[MCS6500 Manual]] page on CLC: https://archive.org/details/mos_microcomputers_programming_manual/page/n40
* [[MCS6500 Manual]] page 25 on CLC: https://archive.org/details/mos_microcomputers_programming_manual/page/n40
* [[Carr]] page on CLC: https://archive.org/details/6502UsersManual/page/n266
* [[Carr]] page 253 on CLC: https://archive.org/details/6502UsersManual/page/n266
* [[Leventhal]] page on CLC: https://archive.org/details/6502-assembly-language-programming/page/n101
* [[Leventhal]] page 3-52 on CLC: https://archive.org/details/6502-assembly-language-programming/page/n101
* snes9x implementation of CLC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1420
* snes9x implementation of CLC: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1420


[[Category:ASM]]
[[Category:ASM]]
[[Category:Inherited from 6502]]
[[Category:Inherited from 6502]]
[[Category:One-byte Instructions]]
[[Category:Implied Instructions]]
[[Category:Two-cycle Instructions]]

Latest revision as of 11:42, 14 December 2023

Basic Info
Addressing Mode Opcode Length Speed
Implied (type 2) 18 1 byte 2 cycles
Flags Affected
N V M X D I Z C
. . . . . . . 0

CLC is a 65x instruction that clears the carry flag.

The 6502 lacks an add-without-carry instruction, so it is important to make sure the carry flag is clear before doing an ADC or else the sum will be one too great.

See Also

External Links