We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
Control Register: Difference between revisions
From SnesLab
(see also) |
(bits cleared upon reset) |
||
(One intermediate revision by the same user not shown) | |||
Line 1: | Line 1: | ||
The '''Control Register''' exists on the [[S-SMP]] and is 8 bits wide. It lives at 00F1h. | The '''Control Register''' exists on the [[S-SMP]] and is 8 bits wide. It lives at 00F1h. Bits 0,1,2,4, and 5 are cleared upon reset. | ||
=== See Also === | === See Also === | ||
* [[Timer Register]] | * [[Timer Register]] | ||
* [[Counter Register]] | |||
=== Reference === | === Reference === |
Latest revision as of 03:48, 17 December 2023
The Control Register exists on the S-SMP and is 8 bits wide. It lives at 00F1h. Bits 0,1,2,4, and 5 are cleared upon reset.
See Also
Reference
- page 3-4-1 of Book II of the official Super Nintendo development manual