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DSP Interface Register: Difference between revisions
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The '''DSP Interface Register''' allows for the [[S-SMP]] to communicate with the [[S-DSP]]. It is 16 bits wide | The '''DSP Interface Register''' allows for the [[S-SMP]] to communicate with the [[S-DSP]]. This register is inside the S-DSP.<sup>[2]</sup> It is 16 bits wide, consisting of two 8-bit subregisters: | ||
* 00F2h holds the target [[DSPRAM]] address | |||
* 00F3h holds the data byte 00F2h points to | |||
Its value is indeterminate upon reset. | Its value is indeterminate upon reset. | ||
=== See Also === | |||
* [[Zero Page]] | |||
=== Reference === | === Reference === | ||
# [https://archive.org/details/SNESDevManual/book1/page/n166%20page%203-6-1 page 3-6-1 of Book I] of the official Super Nintendo development manual | |||
# [https://archive.org/details/SNESDevManual/book1/page/n159 page 3-3-1 of Book I], lbid. | |||
[[Category:Audio]] | [[Category:Audio]] | ||
[[Category:Registers]] | [[Category:Registers]] | ||
Latest revision as of 03:25, 17 December 2023
The DSP Interface Register allows for the S-SMP to communicate with the S-DSP. This register is inside the S-DSP.[2] It is 16 bits wide, consisting of two 8-bit subregisters:
- 00F2h holds the target DSPRAM address
- 00F3h holds the data byte 00F2h points to
Its value is indeterminate upon reset.
See Also
Reference
- page 3-6-1 of Book I of the official Super Nintendo development manual
- page 3-3-1 of Book I, lbid.