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IBT: Difference between revisions

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'''IBT''' is a [[Super FX]] instruction that loads an immediate value.
{| class="wikitable" style="float:right;clear:right;width:40%"
!colspan="8"|Basic Info
|+
|'''Opcode'''
|'''Length'''
|'''ROM Speed'''
|'''RAM Speed'''
|'''Cache Speed'''
|+
|Anpp
|2 bytes
|6 cycles
|6 cycles
|2 cycles
|}


{| class="wikitable" style="float:right;clear:right;width:30%"
{| class="wikitable" style="float:right;clear:right;width:30%"
!colspan="9"|Flags Clobbered
!colspan="9"|Flags Affected
|+
|+
|B
|B
|ALT1
|[[ALT1]]
|ALT2
|[[ALT2]]
|O/V
|[[O/V]]
|S
|S
|CY
|[[CY]]
|Z
|Z
|+
|+
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|.
|.
|}
|}
'''IBT''' (Immediate Byte Data?) is a [[Super FX]] instruction that loads an immediate value into a specified register. Its upper eight bits will be set to the same value as bit 7, effectively loading a signed 8-bit value.


=== See Also ===
=== See Also ===
* [[IWT]]
* [[LDA]]
* [[LDA]]
=== External Links ===
* Official Nintendo documentation on IBT: [https://archive.org/details/SNESDevManual/book2/page/n216 Page 2-9-60 of Book II]


[[Category:ASM]]
[[Category:ASM]]
[[Category:Enhancement Chips]]
[[Category:Super FX]]
[[Category:GSU_Control_Instructions]]
[[Category:Two-byte Instructions]]

Latest revision as of 07:08, 28 November 2023

Basic Info
Opcode Length ROM Speed RAM Speed Cache Speed
Anpp 2 bytes 6 cycles 6 cycles 2 cycles
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . . . .

IBT (Immediate Byte Data?) is a Super FX instruction that loads an immediate value into a specified register. Its upper eight bits will be set to the same value as bit 7, effectively loading a signed 8-bit value.

See Also

External Links