Megaboys Manual

The Super Famicom documentation, scanned by Optiroc of Megaboys.

SFX01, Software Manual

• Contents
• Introduction
• OBJ (Object)
• BG (Background)
• Mosaic
• Rotation/Enlargement/Reduction (BG Mode 7)
• Window (Window Mask)
• Main / Sub Screen
• Screen Addition / Subtraction
• Color Constant Addition/Subtraction
• Color Window
• CG Direct Select
• H-Psuedo 512
• Complementary Multiplication (Signed Multiplication)
• H/V Counter Latch
• Offset Change
• Joy Controller
• Programmable I/O Port
• Absolute Multiplication/Divide
• H/V Count Timer
• DMA (Direct Memory Access)
• General Purpose DMA
• H-DMA
• Interlace
• H- 512 Mode (BG Mode 5 & 6)
• OBJ 33's Lines Over & Priority Order
• CPU Clock & Address Map
• Hardware Configuration
• System Flowchart
• Programming Warnings
• Register Clear (Initial Settings)

SFX02, Register (PPU)

• INIDISP / OBJSEL - page 46
• OAMADDL / OAMADDH / OAM DATA - page 47
• BGMODE / MOSAIC - page 48
• BG1SC / BG2SC / BG3SC / BG4SC - page 49
• BG12NBA / BG34NBA / BG1HOFS BG1VOFS - page 50
• BG2HOFS / BG2VOFS / BG3HOFS / BG3VOFS / BG4HOFS / BG3VOFS / VMAINC - page 51
• VMADDL / VMADDH / VMDATAL / VMDATAH - page 52
• M7SEL - page 53
• M7A / M7B / M7C / M7D / M7X / M7Y - page 54
• CGADD / CGDATA - page 55
• W12SEL / W34SEL / WOBJSEL / WH0 / WH1 / WH2 / WH3 - page 56
• WBLOG / WOBJLOG - page 57
• TM / TS - page 58
• TMW / TSW - page 59
• CGWSEL / CGADSUB - page 60
• COLDATA / SETINI - page 61
• MPYL / MPYM / PYH / SLHV - page 62
• OAMDATA / VMDATAL / VMDATAH - page 63
• CGDATA / OPHCT / OPVCT - page 64
• STAT77 / STAT78 - page 65
• APUIO0 / APUIO1 / APUIO2 / APUIO3 - page 66
• Appendix - page 67
• V-RAM - page 68
• Object Data to be Stored - page 69
• Object Data - page 70
• Object Display - page 71
• Object Mode - page 72
• Mosaic Screen - page 73
• Address Increment Value Set (The Order of Accessing) - page 74
• BG SC Data (Mode 0~6) - page 75
• BG SC Data (Mode 7) - page 76
• CHR Data Construction - page 77
• Offset Change Mode - page 78
• BG Screen - page 79
• Operation (Rotation/Enlargement/Reduction) - page 80
• CG-RAM - page 81
• Window - page 82
• BG & OBJ Priority - page 83
• Screen - page 84
• BG Screen - page 85
• BG Screen - page 86

SFX03, Register (CPU)

• NMITIMEN / WRIO - page 88
• WRMPYA / WRMPYB / WRDIVL / WRDIVH / WRDIVB - page 89
• HTIMEL / HTIMEH / VTIMEL / VTIMEH - page 90
• MDAEN / HDMAEN - page 91
• MEMSEL - page 91a
• RDNMI / TIMEUP - page 92
• HVBJOY / RDIO - page 93
• RDDIVL / RDDIVH / RDMPYL / RDMPYH - page 94
• JOY1L / JOY1H / JOY2L / JOY2H / JOY3L / JOY3H / JOY4L / JOY4H - page 95
• Parameter for Data Transfer - page 96
• B-Bus Address for DMA / Table Address of A-Bus for DMA - page 97
• Data Address Store By H-DMA - page 98
• Table Address of A-Bus By DMA / The Number of Line to be Transferred By H-DMA - page 99
• Appendix - page 100
• General Purpose DMA / H-DMA - page 101
• H-DMA - page 102
• Detect Beginning of V-Blank - page 102a
• Summary of Registers - page 103