We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
PLX: Difference between revisions
From SnesLab
(category pull instructions) |
(Labiak textbook omitted Z flag) |
||
| (6 intermediate revisions by the same user not shown) | |||
| Line 16: | Line 16: | ||
!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|M | |[[M Flag|M]] | ||
|X | |[[X Flag|X]] | ||
|D | |[[Decimal Flag|D]] | ||
|I | |[[I Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
|+ | |+ | ||
| | | | ||
| Line 35: | Line 35: | ||
|} | |} | ||
'''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX takes one additional cycle if the index registers are 16 bits wide. | '''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX increments the [[stack pointer]] before the pull. | ||
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the [[zero flag]]. | |||
===== Cycle Penalty ===== | |||
* PLX takes one additional cycle if the index registers are 16 bits wide. | |||
=== See Also === | === See Also === | ||
| Line 44: | Line 49: | ||
=== External Links === | === External Links === | ||
* [[Eyes & Lichty]] page 487, on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513 | * [[Eyes & Lichty]] page 487, on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513 | ||
* [[Labiak]] page on PLX: https://archive.org/details/Programming_the_65816/page/n181 | * [[Labiak]] page 171 on PLX: https://archive.org/details/Programming_the_65816/page/n181 | ||
* snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156 | * snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156 | ||
| Line 50: | Line 55: | ||
[[Category:65c02 additions]] | [[Category:65c02 additions]] | ||
[[Category:Pull Instructions]] | [[Category:Pull Instructions]] | ||
[[Category:One-byte Instructions]] | |||
[[Category:Four-cycle Instructions]] | |||
Latest revision as of 04:11, 19 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Stack (Pull) | FA | 1 byte | 4 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| . | . | . | . | . | . | |||
PLX (PulL X) is a 65x instruction that pulls the value at the top of the stack into the X index register. PLX increments the stack pointer before the pull.
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the zero flag.
Cycle Penalty
- PLX takes one additional cycle if the index registers are 16 bits wide.
See Also
External Links
- Eyes & Lichty page 487, on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513
- Labiak page 171 on PLX: https://archive.org/details/Programming_the_65816/page/n181
- snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156