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PLX: Difference between revisions
From SnesLab
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{| class="wikitable" style="float:right;clear:right;width:40%" | |||
{| class="wikitable" style="float:right;clear:right;width: | |||
!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
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|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
| | |[[Stack Addressing|Stack]] (Pull) | ||
|FA | |FA | ||
|1 byte | |1 byte | ||
|4 cycles | |4 cycles* | ||
|} | |} | ||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|M | |[[M Flag|M]] | ||
|X | |[[X Flag|X]] | ||
|D | |[[Decimal Flag|D]] | ||
|I | |[[I Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
|+ | |+ | ||
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|} | |} | ||
'''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX increments the [[stack pointer]] before the pull. | |||
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the [[zero flag]]. | |||
===== Cycle Penalty ===== | |||
* PLX takes one additional cycle if the index registers are 16 bits wide. | |||
=== See Also === | |||
* [[PLY]] | |||
* [[PLA]] | |||
* [[PHX]] | |||
=== External Links === | === External Links === | ||
* [[Eyes & Lichty]] page on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513 | * [[Eyes & Lichty]] page 487, on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513 | ||
* [[Labiak]] page on PLX: https://archive.org/details/Programming_the_65816/page/n181 | * [[Labiak]] page 171 on PLX: https://archive.org/details/Programming_the_65816/page/n181 | ||
* snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp# | * snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156 | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:65c02 additions]] | [[Category:65c02 additions]] | ||
[[Category:Pull Instructions]] | |||
[[Category:One-byte Instructions]] | |||
[[Category:Four-cycle Instructions]] | |||
Latest revision as of 04:11, 19 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Stack (Pull) | FA | 1 byte | 4 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| . | . | . | . | . | . | |||
PLX (PulL X) is a 65x instruction that pulls the value at the top of the stack into the X index register. PLX increments the stack pointer before the pull.
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the zero flag.
Cycle Penalty
- PLX takes one additional cycle if the index registers are 16 bits wide.
See Also
External Links
- Eyes & Lichty page 487, on PLX: https://archive.org/details/0893037893ProgrammingThe65816/page/n513
- Labiak page 171 on PLX: https://archive.org/details/Programming_the_65816/page/n181
- snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156