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Program Status Word: Difference between revisions

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The '''Program Status Word''' is an 8-bit register on the [[SPC700]] that stores the value of status flags.  They are typically listed in this order: NVPBHIZC.  More verbosely:
The '''Program Status Word''' is an 8-bit register on the [[SPC700]] that stores the values of status flags.  They are typically listed in this order: NVPBHIZC.  More verbosely:


* Negative Flag
{| class="wikitable"
* overflow Flag
!colspan="2"|
* [[direct page flag]]
|+
* [[Break Flag]]
! Flag Name !! Bit Position
* [[Half-carry flag]]
|+
* [[Interrupt Enable Flag]]
| [[Negative Flag]] || bit 7
* Zero Flag
|+
* Carry flag
| [[Overflow Flag]] || bit 6
|+
| [[Direct Page Flag]] || bit 5
|+
| [[Break Flag]] || bit 4
|+
| [[Half-carry flag]] || bit 3
|+
| [[Interrupt Enable Flag]] || bit 2
|+
| [[Zero Flag]] || bit 1
|+
| [[Carry Flag]] || bit 0
|}
 
Both the [[PUSH]] and [[POP]] commands can operate on the PSW.
 
=== See Also ===
* [[Processor Status Register]]
 
=== Reference ===
* subparagraph 8.1.6, [https://archive.org/details/SNESDevManual/book1/page/n184 page 3-8-6 of Book I] of the official Super Nintendo development manual


[[Category:ASM]]
[[Category:ASM]]
[[Category:SPC700]]
[[Category:SPC700]]
[[Category:Registers]]
[[Category:Flags]]
[[Category:Flags]]

Latest revision as of 14:13, 29 December 2023

The Program Status Word is an 8-bit register on the SPC700 that stores the values of status flags. They are typically listed in this order: NVPBHIZC. More verbosely:

Flag Name Bit Position
Negative Flag bit 7
Overflow Flag bit 6
Direct Page Flag bit 5
Break Flag bit 4
Half-carry flag bit 3
Interrupt Enable Flag bit 2
Zero Flag bit 1
Carry Flag bit 0

Both the PUSH and POP commands can operate on the PSW.

See Also

Reference