We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

SPC700/Waitstates

From SnesLab
Revision as of 17:31, 12 July 2023 by Jeffythedragonslayer (talk | contribs) (rearranged table from 32x8 to 16x16 to reduce distance eye needs to traverse)
Jump to: navigation, search

This table shows how many waitstates the internal cycles of all the SPC700 opcodes have.

00..0F 0 3 0 1 0 0 0 1 0 0 1 0 0 1 0 2
10..1F 2 3 0 3 1 1 1 1 0 0 0 1 0 0 0 1
20..2F 0 3 0 1 0 0 0 1 0 0 1 0 0 1 3 2
30..3F 0 3 0 3 1 1 1 1 0 0 0 1 0 0 0 3
40..4F 0 3 0 1 0 0 0 1 0 0 0 0 0 1 0 3
50..5F 2 3 0 3 1 1 1 1 0 0 0 1 0 0 0 0
60..6F 0 3 0 1 0 0 0 1 0 1 0 0 0 1 2 1
70..7F 0 3 0 3 1 1 1 1 1 1 1 1 0 0 0 1
80..8F 0 3 0 1 0 0 0 1 0 0 1 0 0 0 1 0
90..9F 2 3 0 3 1 1 1 1 0 0 1 1 0 0 10 3
A0..AF 1 3 0 1 0 0 0 1 0 0 0 0 0 0 1 1
B0..BF 0 3 0 3 1 1 1 1 0 0 1 1 0 0 1 1
C0..CF 1 3 0 1 0 0 0 1 0 0 1 0 0 0 1 7
D0..DF 2 3 0 3 1 1 1 1 0 1 0 1 0 0 4 1
E0..EF 0 3 0 1 0 0 0 1 0 0 0 0 0 1 1 0
F0..FF 0 3 0 3 1 1 1 1 0 1 0 1 0 0 3 0

Reference