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STY: Difference between revisions

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(clobbered -> affected)
(additional cycles)
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|8C
|8C
|3 bytes
|3 bytes
|4 cycles
|4 cycles*
|+
|+
|direct page
|direct page
|84
|84
|2 bytes
|2 bytes
|3 cycles
|3 cycles*
|+
|+
|direct page indexed Y
|direct page indexed Y
|96
|96
|2 bytes
|2 bytes
|4 cycles
|4 cycles*
|}
|}


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'''STY''' (Store Y) is a 65x instruction that stores the value of the [[Y index register]].
'''STY''' (Store Y) is a 65x instruction that stores the value of the [[Y index register]].  STY takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]]. In both [[direct page addressing]] modes only, STY takes another additional cycle if the low byte of the [[direct page register]] is nonzero.  


=== See Also ===
=== See Also ===

Revision as of 21:46, 19 November 2023

Basic Info
Addressing Mode Opcode Length Speed
absolute 8C 3 bytes 4 cycles*
direct page 84 2 bytes 3 cycles*
direct page indexed Y 96 2 bytes 4 cycles*
Flags Affected
N V M X D I Z C
. . . . . . . .

STY (Store Y) is a 65x instruction that stores the value of the Y index register. STY takes one additional cycle when the index registers are 16 bits wide, in all addressing modes. In both direct page addressing modes only, STY takes another additional cycle if the low byte of the direct page register is nonzero.

See Also

External Links