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Template:8bit-reg

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Revision as of 14:07, 19 May 2019 by Vitor Vilela (talk | contribs) (Testing a possible dynamic table system for registers. TO DO.)
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D7 D6 D5 D4 D3 D2 D1 D0 Register
SA-1
CPU
IRQ		 SA-1
CPU
RDY B		 SA-1
CPU
RESB		 SA-1
CPU
NMI		 SMEG3 SMEG2 SMEG1 SMEG0 $2200
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