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ROR (Super FX)
From SnesLab
(Redirected from GSU/ROR)
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 97 | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
ROR (Rotate Right) is a Super FX instruction that rotates the value of the source register and carry flag one bit to the right into the destination register. Bit 0 of Sreg is shifted into the carry flag. A total of 17 bits participate in the rotation.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
ROR
Example
Let:
Sreg : R10 Dreg : R12 CY = 1 R10 = 1d4bh (0001 1101 0100 1011b)
After executing ROR:
CY = 1 R12 = 8ea5h (1000 1110 1010 0101b)
The source register itself is not modified despite the arrows in the above image.
See Also
External Links
- Official Nintendo documentation on ROR: 9.76 on page 2-9-105 of Book II
- example: page 2-9-106, lbid.