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PLX: Difference between revisions

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[[Category:65c02 additions]]
[[Category:65c02 additions]]
[[Category:Pull Instructions]]
[[Category:Pull Instructions]]
[[Category:One-byte Instructions]]

Revision as of 06:29, 28 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Stack (Pull) FA 1 byte 4 cycles*
Flags Affected
N V M X D I Z C
. . . . . .

PLX (PulL X) is a 65x instruction that pulls the value at the top of the stack into the X index register.

Cycle Penalty
  • PLX takes one additional cycle if the index registers are 16 bits wide.

See Also

External Links