User contributions for Xetheria

06:0006:00, 25 March 2025 diff hist +88‎ Audio RAM ‎ cannot be accessed directly by 5A22 current
05:5405:54, 25 March 2025 diff hist +5‎ Sound RAM ‎ consolidated double redirect current Tag: Redirect target changed
05:3105:31, 25 March 2025 diff hist +70‎ Interrupt Disable Flag ‎ vblank NMI also ignored current
01:3101:31, 25 March 2025 diff hist −1‎ Write Enable ‎ →‎References: depluralize current

09:1809:18, 24 March 2025 diff hist +14‎ Control Section ‎ one of two main parts current
09:1409:14, 24 March 2025 diff hist +32‎ Register Section ‎ IR could be in control section current
09:0309:03, 24 March 2025 diff hist +29‎ Control Section ‎ official jargon category
09:0309:03, 24 March 2025 diff hist +29‎ Register Section ‎ official jargon category
09:0109:01, 24 March 2025 diff hist +63‎ Control Section ‎ generates signals
08:5808:58, 24 March 2025 diff hist +33‎ Register Section ‎ where the registers live
07:0507:05, 24 March 2025 diff hist +67‎ Eyes & Lichty ‎ →‎Eratta: stack register modified current
06:5606:56, 24 March 2025 diff hist +21‎ Uppermost Page Addressing ‎ see also Uppermost page current
06:4606:46, 24 March 2025 diff hist +154‎ Eyes & Lichty ‎ →‎Eratta: too many zeros
02:5702:57, 24 March 2025 diff hist +77‎ Break Flag ‎ no SEB/CLB current
02:2702:27, 24 March 2025 diff hist +20‎ PLP ‎ see also SEP/REP current
00:1000:10, 24 March 2025 diff hist +109‎ Memory Lock ‎ zero during R,M,W current
00:0500:05, 24 March 2025 diff hist +143‎ ALU ‎ more of what the ALU does current
00:0200:02, 24 March 2025 diff hist +34‎ N instruction register ‎ created page current Tag: New redirect
00:0200:02, 24 March 2025 diff hist +95‎ Timing Control Unit ‎ more info current

23:0723:07, 17 March 2025 diff hist +43‎ BRK ‎ put pbr stuff in right timing current
23:0423:04, 17 March 2025 diff hist +24‎ BRK ‎ when interrupt disable flag set
22:5922:59, 17 March 2025 diff hist +106‎ BRK ‎ status reg: rearranged execution sequence
22:5522:55, 17 March 2025 diff hist +82‎ BRK ‎ pc
21:1121:11, 17 March 2025 diff hist +17‎ Interrupt Request ‎ see also break flag current
21:0621:06, 17 March 2025 diff hist +129‎ Break Flag ‎ →‎References: added reg preservation link
20:2220:22, 17 March 2025 diff hist +80‎ REP ‎ [Xetheria](<httpcitation for mx bits forced to 1 in emulation mode current
20:1920:19, 17 March 2025 diff hist +80‎ SEP ‎ citation for mx bits forced to 1 in emulation mode current
20:0520:05, 17 March 2025 diff hist +71‎ Talk:Break Flag ‎ SEP/REP current
20:0120:01, 17 March 2025 diff hist 0‎ Break Flag ‎ grouped '816 stuff together and spc stuff together

06:1206:12, 15 March 2025 diff hist +141‎ Y Index Register ‎ initial value or close to it current
06:1106:11, 15 March 2025 diff hist +140‎ X Index Register ‎ initial value or close to it current
06:0906:09, 15 March 2025 diff hist +143‎ Accumulator ‎ initial value or close to it current
06:0706:07, 15 March 2025 diff hist +150‎ Stack Pointer ‎ initial value or close to it current
05:5005:50, 15 March 2025 diff hist 0‎ S-SMP ‎ →‎References: bullet -> numbered current
05:4705:47, 15 March 2025 diff hist +18‎ BRK (SPC700) ‎ linkify flags into psw current
05:4605:46, 15 March 2025 diff hist +157‎ Program Status Word ‎ initial value or close to it current
04:1604:16, 15 March 2025 diff hist +1‎ Reset Vector ‎ fixed hyperlink current
04:1604:16, 15 March 2025 diff hist +68‎ Reset Vector ‎ location
04:1004:10, 15 March 2025 diff hist +36‎ Emulation Mode Flag ‎ break flag does not exist in native mode current
04:0904:09, 15 March 2025 diff hist +267‎ Emulation Mode Flag ‎ more reasons to avoid emulation mode
03:3003:30, 15 March 2025 diff hist +25‎ N B accumulator ‎ created page current Tag: New redirect
03:2903:29, 15 March 2025 diff hist +224‎ Emulation Mode Flag ‎ other regs that exist in emulation mode