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TSET1 (SPC700): Difference between revisions
From SnesLab
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=== External Links === | === External Links === | ||
# Official Super Nintendo development manual on TSET1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | # Official Super Nintendo development manual on TSET1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
# section 8.2.3. | # section 8.2.3.2 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | ||
[[Category:ASM]] | [[Category:ASM]] | ||
Revision as of 06:24, 18 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute | 0E | 3 byte | 6 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | ||
TSET1 is an SPC700 instruction that tests and sets memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is also set.
See Also
External Links
- Official Super Nintendo development manual on TSET1: Table C-18 in Appendix C-9 of Book I
- section 8.2.3.2 of page 3-8-8, lbid.