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Instruction Controller: Difference between revisions
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The '''Instruction Controller''' is one of the | The '''Instruction Controller''' is one of the six components of the [[Super FX]]. | ||
It contains the cache pipeline decoder. | It contains the [[cache pipeline decoder]]. It receives input from: | ||
* the [[Game Pak RAM Controller]] | |||
* the [[Game Pak ROM Controller]] | |||
* the [[SNES CPU Interface]] (which it also outputs to) | |||
=== References === | |||
* [https://archive.org/details/SNESDevManual/book2/page/n95 Figure 2-2-1 "GSU Functional Block Diagram" on page 2-2-1] of the official Super Nintendo development manual | |||
* [https://archive.org/details/SNESDevManual/book2/page/n96 page 2-1-2 of Book II], lbid. | |||
[[Category:Super FX]] | [[Category:Super FX]] | ||
Latest revision as of 07:23, 21 December 2023
The Instruction Controller is one of the six components of the Super FX.
It contains the cache pipeline decoder. It receives input from:
- the Game Pak RAM Controller
- the Game Pak ROM Controller
- the SNES CPU Interface (which it also outputs to)
References
- Figure 2-2-1 "GSU Functional Block Diagram" on page 2-2-1 of the official Super Nintendo development manual
- page 2-1-2 of Book II, lbid.