LMULT (Super FX): Difference between revisions

Revision as of 12:11, 22 December 2023


Basic Info
Opcode	Length	ROM Speed	RAM Speed	Cache Speed
3D9F	2 bytes	10 or 14 cycles	10 or 14 cycles	5 or 9 cycles


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.

LMULT is a signed multiplication Super FX instruction. The exact speed depends on the state of the CFGR register.

LMULT utilizes the 8-bit multiplier four times.^[3]

@@ Line 1: / Line 1: @@
-'''LMULT''' is a signed multiplication [[Super FX]] instruction.
+{| class="wikitable" style="float:right;clear:right;width:50%"
+!colspan="8"|Basic Info
+|+
+|'''Opcode'''
+|'''Length'''
+|'''ROM Speed'''
+|'''RAM Speed'''
+|'''Cache Speed'''
+|+
+|3D9F
+|2 bytes
+|10 or 14 cycles
+|10 or 14 cycles
+|5 or 9 cycles
+|}
+{| class="wikitable" style="float:right;clear:right;width:30%"
+!colspan="9"|Flags Affected
+|+
+|B
+|[[ALT1]]
+|[[ALT2]]
+|[[O/V]]
+|S
+|[[CY]]
+|Z
+|+
+|0
+|0
+|0
+|.
+|
+|
+|
+|}
+'''LMULT''' is a signed multiplication [[Super FX]] instruction.  The exact speed depends on the state of the [[CFGR]] register.
+LMULT utilizes the 8-bit multiplier four times.<sup>[3]</sup>
 === See Also ===
 * [[FMULT]]
+* [[UMULT]]
+* [[Partial Product Buffer]]
+=== External Links ===
+# Official Nintendo documentation on LMULT: [https://archive.org/details/SNESDevManual/book2/page/n229 page 2-9-73 of Book II]
+# example: [https://archive.org/details/SNESDevManual/book2/page/n230 page 2-9-74 of Book II], lbid.
+# https://archive.org/details/SNESDevManual/book2/page/n155
 [[Category:ASM]]
-[[Category:Enhancement Chips]]
+[[Category:Super FX]]