AND: Difference between revisions

Revision as of 22:53, 26 June 2024


Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	29	2 bytes	2 cycles*
Absolute	2D	3 bytes	4 cycles*
Absolute Long	2F	4 bytes	5 cycles*
Direct Page	25	2 bytes	3 cycles*
Direct Page Indirect	32	2 bytes	5 cycles*
Direct Page Indirect Long	27	2 bytes	6 cycles*
Absolute Indexed by X	3D	3 bytes	4 cycles*
Absolute Long Indexed by X	3F	4 bytes	5 cycles*
Absolute Indexed by Y	39	3 bytes	4 cycles*
Direct Page Indexed by X	35	2 bytes	4 cycles*
Direct Page Indirect Indexed by X	21	2 bytes	6 cycles*
Direct Page Indirect Indexed by Y	31	2 bytes	5 cycles*
Direct Page Indirect Long Indexed by Y	37	2 bytes	6 cycles*
Stack Relative	23	2 bytes	4 cycles*
Stack Relative Indirect Indexed by Y	33	2 bytes	7 cycles*


Flags Affected
N	V	M	X	D	I	Z	C
	.	.	.	.	.		.

AND is a 65x instruction that performs a logical AND. The conjunction is stored in the accumulator.

In all addressing modes, AND takes one extra cycle when the accumulator is 16 bits wide.
In direct page addressing modes only, AND takes an extra cycle if the low byte of the direct page register is nonzero.
In both Absolute Indexed addressing modes and DP Indirect Indexed by Y admodes, AND takes an extra cycle if adding the index crosses a page boundary.

@@ Line 37: / Line 37: @@
 |6 cycles*
 |+
-|absolute indexed by X
+|[[Absolute Indexed by X]]
 |3D
 |3 bytes
 |4 cycles*
 |+
-|absolute long indexed by X
+|[[Absolute Long Indexed by X]]
 |3F
 |4 bytes
 |5 cycles*
 |+
-|absolute indexed by Y
+|[[Absolute Indexed by Y]]
 |39
 |3 bytes
 |4 cycles*
 |+
-|direct page indexed by X
+|[[Direct Page Indexed by X]]
 |35
 |2 bytes
 |4 cycles*
 |+
-|direct page indirect indexed by X
+|[[Direct Page Indirect Indexed by X]]
 |21
 |2 bytes
 |6 cycles*
 |+
-|direct page indirect indexed by Y
+|[[Direct Page Indirect Indexed by Y]]
 |31
 |2 bytes
 |5 cycles*
 |+
-|direct page indirect long indexed by Y
+|[[Direct Page Indirect Long Indexed by Y]]
 |37
 |2 bytes