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FMULT (Super FX): Difference between revisions
From SnesLab
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!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
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|B | |[[B Flag|B]] | ||
|[[ALT1]] | |[[ALT1]] | ||
|[[ALT2]] | |[[ALT2]] | ||
Revision as of 19:56, 30 June 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Opcode | Length | ROM Speed | RAM Speed | Cache Speed | |||
| 9F | 1 byte | 7 or 11 cycles | 7 or 11 cycles | 4 or 8 cycle | |||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | |||||
FMULT is a Super FX instruction that performs a signed multiplication. The two factors are the source register and R6. The upper 16 bits of the 32-bit product are stored in the destination register. Bit 15 of the product is stored in CY. The lower 15 bits of the product appear to be discarded.
The exact speed depends on the state of the CFGR register. FMULT utilizes the 8-bit multiplier four times.[3]
R4 cannot serve as the destination register.
FMULT shares its multiplication circuit with LMULT.
See Also
External Links
- Official Nintendo documentation on FMULT: Page 2-9-46 of Book II
- example: page 2-9-47, lbid.
- page 2-8-16, lbid.