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BIC (Super FX): Difference between revisions
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==== Example ==== | ==== Example 1 ==== | ||
Let: | Let: | ||
S<sub>reg</sub> : R<sub>2</sub> | S<sub>reg</sub> : R<sub>2</sub> | ||
| Line 60: | Line 60: | ||
After executing BIC R<sub>1</sub>: | After executing BIC R<sub>1</sub>: | ||
R<sub>0</sub> = 4588h (0100 0101 1000 1000b) | R<sub>0</sub> = 4588h (0100 0101 1000 1000b) | ||
==== Example 2 ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>4</sub> | |||
D<sub>reg</sub> : R<sub>5</sub> | |||
R<sub>4</sub> = 364bh (0011 0110 0100 1011b) | |||
After BIC #F is executed: | |||
R<sub>5</sub> = 3640h (0011 0110 0100 0000b) | |||
=== See Also === | === See Also === | ||
Revision as of 21:46, 8 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 3D7n | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Immediate | 3F7n | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | ||||
BIC (BIt Clear mask) is a Super FX instruction that performs a logical AND between the source register and the 1's complement of the operand. The conjunction is stored in the destination register.
Syntax
BIC Rn BIC #n
Example 1
Let:
Sreg : R2 Dreg : R0 R2 = 75ceh (0111 0101 1100 1110b) R1 = 3846h (0011 1000 0100 0110b)
After executing BIC R1:
R0 = 4588h (0100 0101 1000 1000b)
Example 2
Let:
Sreg : R4 Dreg : R5 R4 = 364bh (0011 0110 0100 1011b)
After BIC #F is executed:
R5 = 3640h (0011 0110 0100 0000b)
See Also
External Links
- Official Nintendo documentation on BIC: 9.18 on Page 2-9-22 of Book II
- immediate BIC: 9.19 on page 2-9-23, lbid.