RAMB (Super FX): Difference between revisions

Latest revision as of 00:20, 13 July 2024


Basic Info
Addressing Mode	Opcode	Length	ROM Speed	RAM Speed	Cache Speed
Implied (type 1)	3EDF	2 bytes	6 cycles	6 cycles	2 cycles


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.	.	.	.

RAMB is a Super FX instruction that moves the low byte of the source register into RAMBR.

The source register should be specified in advance using WITH or FROM. Otherwise, R₀ serves as the default.

The ALT0 state is restored.

RAMB

Let:

S_reg : R₃
R₃ = 0170h

After executing RAMB, the RAM bank register becomes 70h.

@@ Line 1: / Line 1: @@
-{| class="wikitable" style="float:right;clear:right;width:40%"
+{| class="wikitable" style="float:right;clear:right;width:50%"
 !colspan="8"|Basic Info
 |+
+|'''Addressing Mode'''
 |'''Opcode'''
 |'''Length'''
@@ Line 8: / Line 9: @@
 |'''Cache Speed'''
 |+
+|[[Implied]] (type 1)
 |3EDF
 |2 bytes
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 |[[Sign Flag|S]]
 |[[CY]]
-|Z
+|[[Zero Flag|Z]]
 |+
 |0
@@ Line 36: / Line 38: @@
 '''RAMB''' is a [[Super FX]] instruction that moves the low byte of the [[source register]] into [[RAMBR]].
+The source register should be specified in advance using [[WITH]] or [[FROM]].  Otherwise, R<sub>0</sub> serves as the default.
+The [[ALT0]] state is restored.
+==== Syntax ====
+<pre>
+RAMB
+</pre>
+==== Example ====
+Let:
+ S<sub>reg</sub> : R<sub>3</sub>
+ R<sub>3</sub> = 0170h
+After executing RAMB, the RAM bank register becomes 70h.
 === See Also ===
 * [[ROMB]]
+* [[ALT2]]
+* [[SMS]]
+* [[SM]]
 === External Links ===
@@ Line 47: / Line 67: @@
 [[Category:Bank Set-up Instructions]]
 [[Category:Two-byte Instructions]]
+[[Category:Expects Sreg/Dreg Prearranged]]