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CLR1 (SPC700): Difference between revisions
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|'''Speed''' | |'''Speed''' | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|12 | |12 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|32 | |32 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|52 | |52 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|72 | |72 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|92 | |92 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|B2 | |B2 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|D2 | |D2 | ||
|2 bytes | |2 bytes | ||
|4 cycles | |4 cycles | ||
|+ | |+ | ||
|[[Direct Page Addressing | Direct Page]] | |[[Direct Page Bit Addressing | Direct Page Bit]] | ||
|F2 | |F2 | ||
|2 bytes | |2 bytes | ||
| Line 49: | Line 49: | ||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="8"|Flags | !colspan="8"|Flags Affected | ||
|+ | |+ | ||
|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|P | |[[Direct Page Flag|P]] | ||
|B | |[[Break Flag|B]] | ||
|H | |[[Half-Carry Flag|H]] | ||
|I | |[[Interrupt Enable Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
|+ | |+ | ||
|. | |. | ||
| Line 70: | Line 70: | ||
|} | |} | ||
'''CLR1''' is an [[SPC700]] command that clears a bit in a [[direct page]] byte. The byte following the opcode determines which byte. The | '''CLR1''' is an [[SPC700]] command that clears a bit in a [[direct page]] byte. The byte following the opcode determines which byte. The most significant 3 bits of the opcode determines which bit within that byte. In Nintendo's manual, the high nybble of the opcode is called y. | ||
No flags are affected. | |||
==== Syntax ==== | |||
<pre> | |||
CLR1 dip. bit | |||
</pre> | |||
=== See Also === | === See Also === | ||
* [[SET1]] | * [[SET1]] | ||
* [[TCLR1]] | * [[TCLR1]] | ||
* [[RMB]] | |||
* [[dip bit]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on CLR1: [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | * Official Nintendo documentation on CLR1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
* subparagraph 8.2.3.1 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | |||
* anomie: https://github.com/yupferris/TasmShiz/blob/8fabc9764c33a7ae2520a76d80ed7220bb939f12/spc700.txt#L375 | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:SPC700]] | [[Category:SPC700]] | ||
[[Category:Bit Operation Commands]] | [[Category:Bit Operation Commands]] | ||
[[Category:Read-Modify-Write Instructions]] | |||
[[Category:Two-byte Instructions]] | |||
Latest revision as of 22:18, 13 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Direct Page Bit | 12 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | 32 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | 52 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | 72 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | 92 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | B2 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | D2 | 2 bytes | 4 cycles | ||||
| Direct Page Bit | F2 | 2 bytes | 4 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | . | . |
CLR1 is an SPC700 command that clears a bit in a direct page byte. The byte following the opcode determines which byte. The most significant 3 bits of the opcode determines which bit within that byte. In Nintendo's manual, the high nybble of the opcode is called y.
No flags are affected.
Syntax
CLR1 dip. bit
See Also
External Links
- Official Nintendo documentation on CLR1: Table C-18 in Appendix C-9 of Book I
- subparagraph 8.2.3.1 of page 3-8-8, lbid.
- anomie: https://github.com/yupferris/TasmShiz/blob/8fabc9764c33a7ae2520a76d80ed7220bb939f12/spc700.txt#L375