AND (Super FX): Difference between revisions

Revision as of 22:33, 13 July 2024


Basic Info
Addressing Mode	Opcode	Length	ROM Speed	RAM Speed	Cache Speed
Immediate	3E7n	2 bytes	6 cycles	6 cycles	2 cycles
Implied (type 1)	7n	1 byte	3 cycles	3 cycles	1 cycle


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.		.

AND is a Super FX instruction that performs a logical AND on the source register and R_n. The conjunction is stored in the destination register. The operand cannot be R₀.

The ALT0 state is restored.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R₀ serves as the default.

Syntax

AND Rn
AND #n

Example 1

AND  R₈   ; R₀ AND R₈ -> R₀
          ; 163ah and 00ffh -> 003ah
FROM R₉   ; set the source reg to R₉
TO   R₁₀  ; set the dest reg to R₁₀
AND  R₇   ; R₉ AND R₇ -> R₁₀
          ; 55aah and ff00h -> 5500h

Example 2

Let:

R₀ = 3e5dh (0011 1110 0101 1101b)

After executing AND #6h:

R₀ = 0004h (0000 0000 0000 0100b)

External Links

Official Nintendo documentation on AND: 9.11 Page 2-9-10 of Book II
AND with immediate addressing: 9.12 Page 2-9-11 of Book II
anomie: https://github.com/yupferris/TasmShiz/blob/8fabc9764c33a7ae2520a76d80ed7220bb939f12/spc700.txt#L319

@@ Line 79: / Line 79: @@
 * Official Nintendo documentation on AND: 9.11 [https://archive.org/details/SNESDevManual/book2/page/n166 Page 2-9-10 of Book II]
 * AND with immediate addressing: 9.12 [https://archive.org/details/SNESDevManual/book2/page/n167 Page 2-9-11 of Book II]
+* anomie: https://github.com/yupferris/TasmShiz/blob/8fabc9764c33a7ae2520a76d80ed7220bb939f12/spc700.txt#L319
 [[Category:ASM]]