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LDB (Super FX): Difference between revisions
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{| class="wikitable" style="float:right;clear:right;width: | {| class="wikitable" style="float:right;clear:right;width:50%" | ||
!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
| Line 8: | Line 9: | ||
|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
|[[Implied Indirect]] | |||
|3D4m | |3D4m | ||
|2 byte | |2 byte | ||
| Line 22: | Line 24: | ||
|[[ALT2]] | |[[ALT2]] | ||
|[[O/V]] | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
| Line 38: | Line 40: | ||
Part of the reason why LDB takes so many cycles is that the GSU waits for data to be loaded from game pak ram. | Part of the reason why LDB takes so many cycles is that the GSU waits for data to be loaded from game pak ram. | ||
The [[ALT0]] state is restored. | |||
The destination register should be specified in advance using [[WITH]] or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
LDB (Rm) | |||
</pre> | |||
where m can be from 0~11 | |||
==== Example ==== | |||
Let: | |||
D<sub>reg</sub> : R<sub>7</sub> | |||
R<sub>1</sub> = 3482h | |||
RAMBR : 70h | |||
(70:3482h) = 51h | |||
After LDB (R<sub>1</sub>) is executed: | |||
R<sub>7</sub> = 0051h | |||
=== See Also === | === See Also === | ||
* [[LDW]] | * [[LDW]] | ||
* [[STB]] | |||
* [[RAMB]] | * [[RAMB]] | ||
* [[ALT1]] | |||
=== External Links === | === External Links === | ||
* Official Super Nintendo development manual on LDB: [https://archive.org/details/SNESDevManual/book2/page/n220 Page 2-9-64 of Book II] | * Official Super Nintendo development manual on LDB: 9.45 on [https://archive.org/details/SNESDevManual/book2/page/n220 Page 2-9-64 of Book II] | ||
* example: [https://archive.org/details/SNESDevManual/book2/page/n221 Page 2-9-65], lbid. | * example: [https://archive.org/details/SNESDevManual/book2/page/n221 Page 2-9-65], lbid. | ||
| Line 50: | Line 73: | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Data Transfer Instructions]] | [[Category:Data Transfer Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 05:20, 16 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied Indirect | 3D4m | 2 byte | 11 cycles | 13 cycles | 6 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
LDB (Load Byte) is a Super FX instruction that loads one byte from the Game Pak and stores it in the low byte of the destination register. The high byte of the destination register is zeroed.
Part of the reason why LDB takes so many cycles is that the GSU waits for data to be loaded from game pak ram.
The ALT0 state is restored.
The destination register should be specified in advance using WITH or TO. Otherwise, R0 serves as the default.
Syntax
LDB (Rm)
where m can be from 0~11
Example
Let:
Dreg : R7 R1 = 3482h RAMBR : 70h (70:3482h) = 51h
After LDB (R1) is executed:
R7 = 0051h
See Also
External Links
- Official Super Nintendo development manual on LDB: 9.45 on Page 2-9-64 of Book II
- example: Page 2-9-65, lbid.