We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
AND (Super FX): Difference between revisions
From SnesLab
(made basic info table shorter) |
(made flags affected more prominent) |
||
| (22 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{| class="wikitable" style="float:right;clear:right;width: | {| class="wikitable" style="float:right;clear:right;width:60%" | ||
!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
| Line 9: | Line 9: | ||
|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
| | |[[Immediate]] | ||
|3E7n | |3E7n | ||
|2 bytes | |2 bytes | ||
| Line 16: | Line 16: | ||
|2 cycles | |2 cycles | ||
|+ | |+ | ||
| | |[[Implied]] (type 1) | ||
|7n | |7n | ||
|1 byte | |1 byte | ||
| Line 27: | Line 27: | ||
!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
| Line 39: | Line 39: | ||
|0 | |0 | ||
|. | |. | ||
| | |S | ||
|. | |. | ||
| | |Z | ||
|} | |} | ||
'''AND''' is a [[Super FX]] instruction that performs a logical AND. | '''AND''' is a [[Super FX]] instruction that performs a logical AND on the [[source register]] and R<sub>n</sub>. The conjunction is stored in the [[destination register]]. The operand cannot be R<sub>0</sub>. | ||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
AND Rn | |||
AND #n | |||
</pre> | |||
==== Example 1 ==== | |||
AND R<sub>8</sub> ; R<sub>0</sub> AND R<sub>8</sub> -> R<sub>0</sub> | |||
; 163ah and 00ffh -> 003ah | |||
FROM R<sub>9</sub> ; set the source reg to R<sub>9</sub> | |||
TO R<sub>10</sub> ; set the dest reg to R<sub>10</sub> | |||
AND R<sub>7</sub> ; R<sub>9</sub> AND R<sub>7</sub> -> R<sub>10</sub> | |||
; 55aah and ff00h -> 5500h | |||
==== Example 2 ==== | |||
Let: | |||
R<sub>0</sub> = 3e5dh (0011 1110 0101 1101b) | |||
After executing AND #6h: | |||
R<sub>0</sub> = 0004h (0000 0000 0000 0100b) | |||
=== See Also === | === See Also === | ||
* [[OR (Super FX)]] | * [[OR (Super FX)]] | ||
* [[XOR (Super FX)]] | |||
* [[BIC (Super FX)]] | * [[BIC (Super FX)]] | ||
* [[ALT2]] | |||
* [[AND]] | |||
* [[AND (SPC700)]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on AND: [https://archive.org/details/SNESDevManual/book2/page/n166 Page 2-9-10 of Book II] | * Official Nintendo documentation on AND: 9.11 [https://archive.org/details/SNESDevManual/book2/page/n166 Page 2-9-10 of Book II] | ||
* AND with immediate addressing: 9.12 [https://archive.org/details/SNESDevManual/book2/page/n167 Page 2-9-11 of Book II] | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Logical Operation Instructions]] | [[Category:Logical Operation Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 18:35, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Immediate | 3E7n | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Implied (type 1) | 7n | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | . | Z | ||
AND is a Super FX instruction that performs a logical AND on the source register and Rn. The conjunction is stored in the destination register. The operand cannot be R0.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
AND Rn AND #n
Example 1
AND R8 ; R0 AND R8 -> R0
; 163ah and 00ffh -> 003ah
FROM R9 ; set the source reg to R9
TO R10 ; set the dest reg to R10
AND R7 ; R9 AND R7 -> R10
; 55aah and ff00h -> 5500h
Example 2
Let:
R0 = 3e5dh (0011 1110 0101 1101b)
After executing AND #6h:
R0 = 0004h (0000 0000 0000 0100b)
See Also
External Links
- Official Nintendo documentation on AND: 9.11 Page 2-9-10 of Book II
- AND with immediate addressing: 9.12 Page 2-9-11 of Book II