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DIV2 (Super FX): Difference between revisions
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''' | {| class="wikitable" style="float:right;clear:right;width:50%" | ||
!colspan="8"|Basic Info | |||
|+ | |||
|'''Addressing Mode''' | |||
|'''Opcode''' | |||
|'''Length''' | |||
|'''ROM Speed''' | |||
|'''RAM Speed''' | |||
|'''Cache Speed''' | |||
|+ | |||
|[[Implied]] (type 1) | |||
|3D96 | |||
|2 bytes | |||
|6 cycles | |||
|6 cycles | |||
|2 cycles | |||
|} | |||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
| Line 16: | Line 32: | ||
|0 | |0 | ||
|. | |. | ||
| | |S | ||
| | |CY | ||
| | |Z | ||
|} | |} | ||
'''DIV2''' (DIVide by 2) is a [[Super FX]] instruction that shifts the value of the [[source register]]'s bits one place to the right while also leaving the most significant bit unchanged, storing the quotient in the [[destination register]]. The source register itself is left unchanged. Unlike [[ASR]], the output becomes zero if the input is 0xFFFF. | |||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
DIV2 | |||
</pre> | |||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>7</sub> | |||
D<sub>reg</sub> : R<sub>2</sub> | |||
R<sub>7</sub> = 4635h (0100 0110 0011 0101b) | |||
CY = 0 | |||
After executing DIV2: | |||
R<sub>7</sub> = 231Ah (0010 0011 0001 1010b) | |||
CY = 1 | |||
=== See Also === | === See Also === | ||
* [[ASL]] | * [[ASL]] | ||
* [[ASR]] | * [[ASR]] | ||
* [[LSR (Super FX)]] | |||
* [[LSR (SPC700)]] | |||
* [[LSR]] | * [[LSR]] | ||
* [[DIV (SPC700)]] | |||
* [[ALT1]] | |||
=== External Links === | |||
* Official Nintendo documentation on DIV2: 9.32 on [https://archive.org/details/SNESDevManual/book2/page/n200 page 2-9-44 of Book II] | |||
* example: [https://archive.org/details/SNESDevManual/book2/page/n201 page 2-9-45], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category: | [[Category:Super FX]] | ||
[[Category:Arithmetic Operation Instructions]] | |||
[[Category:Two-byte Instructions]] | |||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 18:44, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 3D96 | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
DIV2 (DIVide by 2) is a Super FX instruction that shifts the value of the source register's bits one place to the right while also leaving the most significant bit unchanged, storing the quotient in the destination register. The source register itself is left unchanged. Unlike ASR, the output becomes zero if the input is 0xFFFF.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
DIV2
Example
Let:
Sreg : R7 Dreg : R2 R7 = 4635h (0100 0110 0011 0101b) CY = 0
After executing DIV2:
R7 = 231Ah (0010 0011 0001 1010b) CY = 1
See Also
External Links
- Official Nintendo documentation on DIV2: 9.32 on page 2-9-44 of Book II
- example: page 2-9-45, lbid.