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FMULT (Super FX): Difference between revisions
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{| class="wikitable" style="float:right;clear:right;width: | {| class="wikitable" style="float:right;clear:right;width:50%" | ||
!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
| Line 8: | Line 9: | ||
|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
|[[Implied]] (type 1) | |||
|9F | |9F | ||
|1 byte | |1 byte | ||
|7 or 11 cycles | |7 or 11 cycles | ||
|7 or 11 cycles | |7 or 11 cycles | ||
|4 or 8 | |4 or 8 cycles | ||
|} | |} | ||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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|0 | |0 | ||
|. | |. | ||
| | |S | ||
| | |CY | ||
| | |Z | ||
|} | |} | ||
'''FMULT''' is a [[Super FX]] instruction that performs a signed multiplication. | '''FMULT''' (Fractional Multiply) is a [[Super FX]] instruction that performs a signed multiplication. The two factors are the [[source register]] and R<sub>6</sub>. The upper 16 bits of the 32-bit product are stored in the [[destination register]]. Bit 15 of the product is stored in [[CY]]. The lower 15 bits of the product appear to be discarded. | ||
The exact speed depends on the state of the [[CFGR]] register. FMULT utilizes the 8-bit multiplier four times.<sup>[3]</sup> | |||
R<sub>4</sub> cannot serve as the destination register, but any other register from R<sub>0</sub> to R<sub>15</sub> can. If R<sub>4</sub> is specified as the destination register anyway, the product will simply not be written to it and will be lost instead.<sup>[3]</sup> | |||
FMULT shares its multiplication circuit with [[LMULT]]. The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
FMULT | |||
</pre> | |||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>5</sub> | |||
D<sub>reg</sub> : R<sub>2</sub> | |||
R<sub>5</sub> = 4aaah | |||
R<sub>6</sub> = daabh | |||
After executing FMULT: | |||
R<sub>2</sub> = f51ch | |||
and the carry flag and [[sign flag]] are set | |||
=== See Also === | === See Also === | ||
* [[UMULT]] | * [[UMULT]] | ||
* [[MULT]] | * [[MULT]] | ||
* [[Partial Product Buffer]] | |||
* [[DIV2]] | |||
=== External Links === | === External Links === | ||
# Official Nintendo documentation on FMULT: 9.33 on [https://archive.org/details/SNESDevManual/book2/page/n202 Page 2-9-46 of Book II] | |||
# example: [https://archive.org/details/SNESDevManual/book2/page/n203 page 2-9-47], lbid. | |||
# 8.2 "Multiplication Instructions" on [https://archive.org/details/SNESDevManual/book2/page/n155 page 2-8-16], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Arithmetic Operation Instructions]] | [[Category:Arithmetic Operation Instructions]] | ||
[[Category:One-byte Instructions]] | |||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 18:44, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 9F | 1 byte | 7 or 11 cycles | 7 or 11 cycles | 4 or 8 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
FMULT (Fractional Multiply) is a Super FX instruction that performs a signed multiplication. The two factors are the source register and R6. The upper 16 bits of the 32-bit product are stored in the destination register. Bit 15 of the product is stored in CY. The lower 15 bits of the product appear to be discarded.
The exact speed depends on the state of the CFGR register. FMULT utilizes the 8-bit multiplier four times.[3]
R4 cannot serve as the destination register, but any other register from R0 to R15 can. If R4 is specified as the destination register anyway, the product will simply not be written to it and will be lost instead.[3]
FMULT shares its multiplication circuit with LMULT. The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
FMULT
Example
Let:
Sreg : R5 Dreg : R2 R5 = 4aaah R6 = daabh
After executing FMULT:
R2 = f51ch
and the carry flag and sign flag are set
See Also
External Links
- Official Nintendo documentation on FMULT: 9.33 on Page 2-9-46 of Book II
- example: page 2-9-47, lbid.
- 8.2 "Multiplication Instructions" on page 2-8-16, lbid.