We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

MERGE (Super FX): Difference between revisions

From SnesLab
Jump to: navigation, search
(General regs)
(made flags affected more prominent)
Line 31: Line 31:
|0
|0
|0
|0
|
|O/V
|
|S
|
|CY
|
|Z
|}
|}



Revision as of 19:24, 30 July 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 70 1 byte 3 cycles 3 cycles 1 cycle
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 O/V S CY Z

MERGE is a Super FX instruction that merges the high bytes of two specific general registers into the destination register.

The high byte of Dreg comes from R7. The low byte of Dreg comes from R8.

The official documentation has several bits labeled "B" not 'D" below the "Flags affected" table.[1]

The ALT0 state is restored.

The destination register should be specified in advance using WITH or TO. Otherwise, R0 serves as the default.

Syntax

MERGE

Example

Let:

Dreg : R9
R7 = 05aah
R8 = fc33h

After executing MERGE:

R9 = 05fch

and the sign, overflow, carry, and zero flags are set

gsu merge.png

See Also

External Links