We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
CLD: Difference between revisions
From SnesLab
(→External Links: hid archive URL for MCS) |
(→External Links: hid archive URL for Leventhal) |
||
Line 53: | Line 53: | ||
* 3.3.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n42 page 27] on CLD | * 3.3.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n42 page 27] on CLD | ||
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n267 page 254] on CLD | * [[Carr]], [https://archive.org/details/6502UsersManual/page/n267 page 254] on CLD | ||
* [[Leventhal]] | * [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n102 page 3-53] on CLD | ||
* snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434 | * snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434 | ||
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1 | * Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1 |
Revision as of 03:01, 8 August 2024
Basic Info | |||||||
---|---|---|---|---|---|---|---|
Addressing Mode | Opcode | Length | Speed | ||||
Implied (type 2) | D8 | 1 byte | 2 cycles |
Flags Affected | ||||||||
---|---|---|---|---|---|---|---|---|
N | V | M | X | D | I | Z | C | |
. | . | . | . | 0 | . | . | . |
CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode so ADC and SBC will operate normally.
Syntax
CLD
See Also
External Links
- Eyes & Lichty, page 442 on CLD
- Labiak, page 131 on CLD
- 3.3.2 on MCS6500 Manual, page 27 on CLD
- Carr, page 254 on CLD
- Leventhal, page 3-53 on CLD
- snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434
- Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1