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CACHE (Super FX): Difference between revisions

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(see also cache ram)
 
(12 intermediate revisions by the same user not shown)
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!colspan="8"|Basic Info
!colspan="8"|Basic Info
|+
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Opcode'''
|'''Length'''
|'''Length'''
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|'''Cache Speed'''
|'''Cache Speed'''
|+
|+
|[[Implied]] (type 2)
|02
|02
|1 byte
|1 byte
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!colspan="9"|Flags Affected
!colspan="9"|Flags Affected
|+
|+
|B
|[[B Flag|B]]
|[[ALT1]]
|[[ALT1]]
|[[ALT2]]
|[[ALT2]]
|[[O/V]]
|[[O/V]]
|S
|[[Sign Flag|S]]
|[[CY]]
|[[CY]]
|Z
|[[Zero Flag|Z]]
|+
|+
|0
|0
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|}
|}


'''CACHE''' is a [[Super FX]] instruction that might reset all cache flags.
'''CACHE''' is a [[Super FX]] instruction that might reset all cache flags. If the [[cache base register]] is equal to R<sub>15</sub> & 0fff0h, nothing happens.  Otherwise, set the cache base register to R<sub>15</sub> & 0fff0h and reset all cache flags.
 
The [[ALT0]] state is restored.
 
==== Syntax ====
<pre>
CACHE
</pre>


=== See Also ===
=== See Also ===
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=== External Links ===
=== External Links ===
* Official Nintendo documentation on CACHE: [https://archive.org/details/SNESDevManual/book2/page/n194 Page 2-9-38 of Book II]
* Official Nintendo documentation on CACHE: 9.27 on [https://archive.org/details/SNESDevManual/book2/page/n194 page 2-9-38 of Book II]
* cautions for 7.1.1 on [https://archive.org/details/SNESDevManual/book2/page/n135 page 2-7-1 of Book II]


[[Category:ASM]]
[[Category:ASM]]

Latest revision as of 01:47, 12 August 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 2) 02 1 byte 3 or 4 cycles 3 or 4 cycles 1 cycle
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . . . .

CACHE is a Super FX instruction that might reset all cache flags. If the cache base register is equal to R15 & 0fff0h, nothing happens. Otherwise, set the cache base register to R15 & 0fff0h and reset all cache flags.

The ALT0 state is restored.

Syntax

CACHE

See Also

External Links