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Control Register: Difference between revisions
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The '''Control Register''' | The '''Control Register''' is 8 bits wide on the [[S-SMP]] and lives at 00F1h. Bits 0 to 5 are cleared upon reset. | ||
=== See Also === | === See Also === | ||
* [[Timer Register]] | * [[Timer Register]] | ||
* [[Counter Register]] | |||
=== Reference === | === Reference === | ||
* [https://archive.org/details/SNESDevManual/book1/page/n161 page 3-4-1 of Book | * Chapter 4, "Control Register" on [https://archive.org/details/SNESDevManual/book1/page/n161 page 3-4-1 of Book I] of the official Super Nintendo development manual | ||
[[Category:Registers]] | [[Category:Registers]] | ||
[[Category:Audio]] | [[Category:Audio]] | ||
[[Category:SPC700]] | |||
Latest revision as of 00:14, 15 August 2024
The Control Register is 8 bits wide on the S-SMP and lives at 00F1h. Bits 0 to 5 are cleared upon reset.
See Also
Reference
- Chapter 4, "Control Register" on page 3-4-1 of Book I of the official Super Nintendo development manual