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Program Bank Register: Difference between revisions
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The '''Program Bank Register''' (PBR or K) | The '''Program Bank Register''' (PBR or K) tells the [[65c816]] which [[bank]] to fetch the next opcode from. It is 8 bits wide and is cleared to zero on reset.<sup>[2]</sup> [[PHK]] pushes it onto the [[stack]], but there is no PLK to pull it. | ||
PBR is affected only by:<sup>[4]</sup> | PBR is affected only by:<sup>[4]</sup> | ||
Revision as of 00:20, 17 August 2024
The Program Bank Register (PBR or K) tells the 65c816 which bank to fetch the next opcode from. It is 8 bits wide and is cleared to zero on reset.[2] PHK pushes it onto the stack, but there is no PLK to pull it.
PBR is affected only by:[4]
Incrementing the program counter past FFFFh does not affect PBR.[4]
There is also a program bank register on the GSU.[1] It can be used to specify any mapped bank address.[3]
See Also
References
- paragraph 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- Figure 2-3-2 Super FX Memory Map on page 2-3-4 of Book II
- section 3.4 Program Address Space of 65c816 datasheet