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Direct Page Register: Difference between revisions
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=== References === | === References === | ||
# page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf | # page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
# page 7, lbid. | # section 2.6 on page 7, lbid. | ||
# [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/53 page 53] | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Registers]] | [[Category:Registers]] | ||
[[Category:65c816 additions]] | [[Category:65c816 additions]] | ||
Latest revision as of 01:12, 17 August 2024
The Direct Page Register exists on the 65c816 and is 16 bits wide.[1] It holds current the location of the direct page.
The direct page register is cleared to point to the zero page on reset.[2]
Its value can be pushed to the stack with PHD and pulled off the stack with PLD.
It can be transferred to and from the full 16 bit accumulator with TCD and TDC.
References
- page 5 of the official 65c816 datasheet: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- section 2.6 on page 7, lbid.
- Eyes & Lichty, page 53