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Machine Cycle: Difference between revisions

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A '''Machine Cycle''' is one tick of the [[5A22]].
A '''Machine Cycle''' is one tick of the [[5A22]]. It may be configured to take 6, 8, or 12 [[master clock]] cycles.  In the SNES scene, we call the 6:1 configuration [[fastROM]] and the 8:1 configuration [[slowROM]].  The 5A22 decides which configuration to use depending on the address that is on the 65c816's address bus, and clocks the '816 clock input accordingly.
 
Multiplication takes about 8 machine cycles and division takes about 16.<sup>[3]</sup>
 
[[File:master clock divider speeds.png]]


=== See Also ===
=== See Also ===
* [[Internal Cycle]]
* [[Internal Cycle]]
* [[FastROM]]
* [[STP]]
* [[SlowROM]]
* [[Master Clock]]


=== References ===
=== References ===
* last bullet point under 13.2 of [https://archive.org/details/SNESDevManual/book1/page/n78 page 2-13-1 of Book I] of the official Super Nintendo development manual
# last bullet point under 13.2 of [https://archive.org/details/SNESDevManual/book1/page/n78 page 2-13-1 of Book I] of the official Super Nintendo development manual
* Figure 3-4-2 "Clear Timing" on [https://archive.org/details/SNESDevManual/book1/page/n161 page 3-4-1 of Book I], lbid.
# Figure 3-4-2 "Clear Timing" on [https://archive.org/details/SNESDevManual/book1/page/n161 page 3-4-1 of Book I], lbid.
* https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/cycles
# 15.2 Absolute Multiplication/Division on [https://archive.org/details/SNESDevManual/book1/page/n81 page 2-15-1 on Book I], lbid.
https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/cycles


[[Category:SNES Hardware]]
[[Category:SNES Hardware]]
[[Category:Official Jargon]]
[[Category:Official Jargon]]
[[Category:Inherited from 6502]]
[[Category:Timing]]

Latest revision as of 13:45, 21 October 2024

A Machine Cycle is one tick of the 5A22. It may be configured to take 6, 8, or 12 master clock cycles. In the SNES scene, we call the 6:1 configuration fastROM and the 8:1 configuration slowROM. The 5A22 decides which configuration to use depending on the address that is on the 65c816's address bus, and clocks the '816 clock input accordingly.

Multiplication takes about 8 machine cycles and division takes about 16.[3]

master clock divider speeds.png

See Also

References

  1. last bullet point under 13.2 of page 2-13-1 of Book I of the official Super Nintendo development manual
  2. Figure 3-4-2 "Clear Timing" on page 3-4-1 of Book I, lbid.
  3. 15.2 Absolute Multiplication/Division on page 2-15-1 on Book I, lbid.
  4. https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/cycles