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TCLR1 (SPC700): Difference between revisions

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|4E
|4E
|3 byte
|3 byte
|3 cycles
|6 cycles
|}
|}



Revision as of 00:34, 7 May 2023

TCLR1 is an SPC700 instruction that tests and clears bits.

Basic Info
Addressing Mode Opcode Length Speed
implied 4E 3 byte 6 cycles
Flags Clobbered
N V P B H I Z C
. . . . . .

See Also