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DIV2 (Super FX): Difference between revisions

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(moved tables up)
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* [[ASR]]
* [[ASR]]
* [[LSR]]
* [[LSR]]
* [[DIV (SPC700)]]


=== External Links ===
=== External Links ===

Revision as of 23:00, 18 July 2023

Basic Info
Opcode Length ROM Speed RAM Speed Cache Speed
3D96 2 bytes 6 cycles 6 cycles 2 cycles
Flags Clobbered
B ALT1 ALT2 O/V S CY Z
0 0 0 .

DIV2 (DIVide by 2) is a Super FX instruction that shifts a register's bits one place to the right while also leaving the most significant bit unchanged. Unlike ASR, the output becomes zero if the input is 0xFFFF.

See Also

External Links