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XCE: Difference between revisions

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(type 2 admode)
Line 7: Line 7:
|'''Speed'''
|'''Speed'''
|+
|+
|implied
|implied (type 2)
|FB
|FB
|1 byte
|1 byte

Revision as of 00:38, 19 July 2023

Basic Info
Addressing Mode Opcode Length Speed
implied (type 2) FB 1 byte 2 cycles
Flags Clobbered
N V M X D I Z C E
. . . . .

XCE is an instruction that exchanges the carry and emulation bits. It typically appears soon after the Reset Vector following a CLC, to switch the S-CPU into 65c816 native mode.

See Also

External Links