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LDW (Super FX): Difference between revisions
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!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
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|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
|[[Implied Indirect]] | |||
|4m | |4m | ||
|1 byte | |1 byte | ||
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!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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'''LDW''' (Load Word) is a [[Super FX]] instruction that loads one word from the [[Game Pak]]. | '''LDW''' (Load Word) is a [[Super FX]] instruction that loads one word from the [[Game Pak]] into the [[destination register]]. The cycle times recorded here include the time spent while the load is happening, when the GSU is in the wait state. | ||
The [[ALT0]] state is restored. | |||
The destination registers should be specified in advance using [[WITH]] or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
LDW (Rm) | |||
</pre> | |||
where m can be from 0~11 | |||
==== Example ==== | |||
Let: | |||
D<sub>reg</sub> : R<sub>5</sub> | |||
R<sub>3</sub> = 6480h | |||
(70:6480h) = C0h | |||
RAMBR = 70h | |||
After executing LDW (R<sub>3</sub>): | |||
R<sub>5</sub> = C02eh | |||
=== See Also === | === See Also === | ||
* [[LDB]] | * [[LDB]] | ||
* [[STW]] | |||
* [[RAMB]] | |||
=== External Links === | === External Links === | ||
* Official Super Nintendo development manual on LDW: [https://archive.org/details/SNESDevManual/book2/page/n222 Page 2-9-66 of Book II] | * Official Super Nintendo development manual on LDW: 9.46 on [https://archive.org/details/SNESDevManual/book2/page/n222 Page 2-9-66 of Book II] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Data Transfer Instructions]] | [[Category:Data Transfer Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 05:20, 16 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied Indirect | 4m | 1 byte | 10 cycles | 12 cycles | 7 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
LDW (Load Word) is a Super FX instruction that loads one word from the Game Pak into the destination register. The cycle times recorded here include the time spent while the load is happening, when the GSU is in the wait state.
The ALT0 state is restored.
The destination registers should be specified in advance using WITH or TO. Otherwise, R0 serves as the default.
Syntax
LDW (Rm)
where m can be from 0~11
Example
Let:
Dreg : R5 R3 = 6480h (70:6480h) = C0h RAMBR = 70h
After executing LDW (R3):
R5 = C02eh
See Also
External Links
- Official Super Nintendo development manual on LDW: 9.46 on Page 2-9-66 of Book II