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ADC (Super FX): Difference between revisions
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|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
| | |[[Implied]] (type 1) | ||
| | |3D5n | ||
|2 bytes | |2 bytes | ||
|6 cycles | |6 cycles | ||
|6 cycles | |6 cycles | ||
|2 | |2 cycles | ||
|+ | |+ | ||
|[[Immediate]] | |[[Immediate]] | ||
| Line 21: | Line 21: | ||
|6 cycles | |6 cycles | ||
|6 cycles | |6 cycles | ||
|2 | |2 cycles | ||
|} | |} | ||
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!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|[[ALT1]] | |[[ALT1]] | ||
|[[ALT2]] | |[[ALT2]] | ||
|[[O/V]] | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
|0 | |0 | ||
|0 | |0 | ||
| | |O/V | ||
| | |S | ||
| | |CY | ||
| | |Z | ||
|} | |} | ||
'''ADC''' (Add with carry) is a [[Super FX]] instruction that performs an addition. The [[source register]] is always the first addend. The second addend may be any of the 16 R registers or an immediate value. The third addend is [[CY]]. The sum is stored in the destination register. | '''ADC''' (Add with carry) is a [[Super FX]] instruction that performs an addition. The [[source register]] is always the first addend. The second addend may be any of the 16 R registers or an immediate value. The third addend is [[CY]]. The sum is stored in the [[destination register]]. | ||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
ADC Rn | |||
ADC #n | |||
</pre> | |||
==== Example 1 ==== | |||
ADC R<sub>1</sub> ; R<sub>0</sub> + R<sub>1</sub> + CY -> R<sub>0</sub> | |||
WITH R<sub>2</sub> ; set the source/destination regs to R<sub>2</sub> | |||
ADC R<sub>3</sub> ; R<sub>2</sub> + R<sub>3</sub> + CY -> R<sub>2</sub> | |||
ADC R<sub>2</sub> ; R<sub>0</sub> + R<sub>2</sub> + CY -> R<sub>0</sub> | |||
==== Example 2 ==== | |||
ADC #9h ; R<sub>0</sub> + 0009h + CY -> R<sub>0</sub> | |||
FROM R<sub>3</sub> ; set the source reg to R<sub>3</sub> | |||
ADC #5h ; R<sub>3</sub> + 0005h + CY -> R<sub>0</sub> | |||
ADC #0ah ; R<sub>0</sub> + 000ah + CY -> R<sub>0</sub> | |||
=== See Also === | === See Also === | ||
* [[ADD]] | * [[ADD]] | ||
* [[ADC]] | * [[ADC]] (65c816) | ||
* [[SUB]] | * [[SUB]] | ||
* [[ALT1]] | |||
* [[ALT3]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on ADC: [https://archive.org/details/SNESDevManual/book2/page/n159 Page 2-9-3 of Book II] | * Official Nintendo documentation on ADC: [https://archive.org/details/SNESDevManual/book2/page/n159 Page 2-9-3 of Book II] | ||
* ADC with immediate addressing: [https://archive.org/details/SNESDevManual/book2/page/n160 Page 2-9-4 of Book II], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Arithmetic Operation Instructions]] | [[Category:Arithmetic Operation Instructions]] | ||
[[Category:Two-byte Instructions]] | |||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 18:30, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 3D5n | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Immediate | 3F5n | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | O/V | S | CY | Z | ||
ADC (Add with carry) is a Super FX instruction that performs an addition. The source register is always the first addend. The second addend may be any of the 16 R registers or an immediate value. The third addend is CY. The sum is stored in the destination register.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
ADC Rn ADC #n
Example 1
ADC R1 ; R0 + R1 + CY -> R0 WITH R2 ; set the source/destination regs to R2 ADC R3 ; R2 + R3 + CY -> R2 ADC R2 ; R0 + R2 + CY -> R0
Example 2
ADC #9h ; R0 + 0009h + CY -> R0 FROM R3 ; set the source reg to R3 ADC #5h ; R3 + 0005h + CY -> R0 ADC #0ah ; R0 + 000ah + CY -> R0
See Also
External Links
- Official Nintendo documentation on ADC: Page 2-9-3 of Book II
- ADC with immediate addressing: Page 2-9-4 of Book II, lbid.