TSET1 (SPC700): Difference between revisions

Latest revision as of 17:41, 11 August 2024


Basic Info
Addressing Mode	Opcode	Length	Speed
Absolute	0E	3 bytes	6 cycles


Flags Affected
N	V	P	B	H	I	Z	C
N	.	.	.	.	.	Z	.

TSET1 is an SPC700 instruction that tests and sets memory bits using the accumulator. For every set bit in the accumulator, TSET1 sets the corresponding memory bit. In other words, a logical OR is performed.

Syntax

TSET1 !abs

Where abs is any address in the whole 64K bank of ARAM.

External Links

Official Super Nintendo development manual on TSET1: Table C-18 in Appendix C-9 of Book I
subparagraph 8.2.3.2 of page 3-8-8, lbid.
anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L607

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 |[[Absolute Addressing | Absolute]]
 |0E
-|3 byte
+|3 bytes
 |6 cycles
 |}
@@ Line 25: / Line 25: @@
 |[[Carry Flag|C]]
 |+
-|
+|N
 |.
 |.
@@ Line 31: / Line 31: @@
 |.
 |.
-|
+|Z
 |.
 |}
-'''TSET1''' is an [[SPC700]] instruction that tests and sets memory bits using the [[accumulator]].  For every set bit in the accumulator, the corresponding memory bit is also set.
+'''TSET1''' is an [[SPC700]] instruction that tests and sets memory bits using the [[accumulator]].  For every set bit in the accumulator, TSET1 sets the corresponding memory bit.  In other words, a logical OR is performed.
+==== Syntax ====
+<pre>
+TSET1 !abs
+</pre>
+Where abs is any address in the whole 64K [[bank]] of [[ARAM]].
 === See Also ===
@@ Line 44: / Line 50: @@
 === External Links ===
 # Official Super Nintendo development manual on TSET1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I]
-# [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid.
+# subparagraph 8.2.3.2 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid.
+# anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L607
 [[Category:ASM]]